Display device

ABSTRACT

The present invention is intended to suppress power consumption of an EL display. In accordance with the brightness of an image to be displayed in a pixel portion, the contrast of the image is determined whether to be inverted or not, and the number of bits of the digital video signal to be input into the pixel portion is reduced, and the magnitude of a current to flow through the EL element is allowed to be maintained at a constant level even when a temperature of an EL layer changes by providing the EL display with another EL element to be used for monitoring a temperature.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a display panel in which a lightemitting element formed on a substrate is sealed between the substrateand a cover member. In addition, the present invention also relates to adisplay module in which an IC chip is mounted on the above-mentioneddisplay panel. It should be noted that in the present specification, thedisplay panel and the display module are collectively referred to as thelight emitting device. The present invention further relates to anelectronic apparatus that employs the above-mentioned light emittingdevice.

[0003] 2. Description of the Related Art

[0004] Recently, techniques for forming a TFT on a substrate has beengreatly advanced, and much developments have been made to apply thosetechniques to an active-matrix type display device. In particular, a TFTemploying a poly-crystalline silicon film can operate at a higher speedsince a field effect mobility (simply referred to as the mobility)thereof is larger than that of a TFT employing the conventionalamorphous silicon film. Thus, it becomes possible to control pixels bymeans of a driver circuit formed on the same substrate as the pixels.Such the pixels was conventionally controlled by means of a drivercircuit provided at the outside of the substrate.

[0005] The active-matrix type display device as mentioned above canexhibit various advantages such as a reduced fabricating cost,miniaturization of the display device, an increased fabricating yield, areduced throughput or the like, by providing various circuits andelements on the identical substrate.

[0006] Furthermore, developments of an active-matrix type light emittingdevice having light emitting elements as a self-emission type elementhave been actively conducted. Such a light emitting device is alsoreferred to as an Organic EL Display (OELD) or an Organic Light EmittingDiode (OLED).

[0007] Unlike a liquid crystal display, the light emitting device is ofthe self-emission type. The light emitting element has a structure inwhich a layer containing an organic compound (hereinafter referred to asthe organic compound layer) that allows luminescence to be generated byapplying an electrical field thereto is interposed between a pair ofelectrodes (an anode and a cathode). The organic compound layer usuallyhas a layered structure. Typical examples therefor include a layeredstructure of “a hole transportation layer/a light emitting layer/anelectron transportation layer” proposed by Tang et al. of Eastman KodakCo. This structure has a high luminous efficiency, and most of lightemitting devices about which research and development activities arecurrently being progressed employ this structure.

[0008] Although a luminescence in an organic compound includes a singletexcitation (fluorescence) and a triplet excitation (phosphorescence),the light emitting device of the present invention can use one or bothof the above luminescence.

[0009] Alternatively, a layered structure in which a hole injectionlayer/a hole transportation layer/a light emitting layer/an electrontransportation layer, or a hole injection layer/a hole transportationlayer a light emitting layer an electron transportation layer/anelectron injection layer are formed on an anode in these orders may beused. Furthermore, fluorescent dyes or the like may be doped into thelight emitting layer.

[0010] In the present specification, all of the layers to be disposedbetween the cathode and the anode are collectively referred to as theorganic compound layer. Accordingly, all of the above-mentioned layerssuch as the hole injection layer, the hole transportation layer, thelight emitting layer, the electron transportation layer, the electroninjection layer or the like are included in the organic compound layer.

[0011] A predetermined voltage is applied to the organic compound layermade of the above-mentioned structure via the pair of electrodes, andthus recombination of carriers occurs in the light emitting layer,thereby resulting in light emission. In the present specification, whenthe light emitting element emits light, the light emitting element isexpressed as being driven. In addition, in the present specification,the light emitting element composed of an anode, an organic compoundlayer, and a cathode is referred to as the light emitting element.

[0012] Since the light emitting device is not required to employ a backlight, a thickness and a weight of the display itself can be suppressed,as compared to a liquid crystal display. For that reason, the lightemitting device has come to be used as a display section of a portableinformation terminal (a mobile computer, a portable telephone, aportable game apparatus, an electronic book or the like), instead of theliquid crystal display.

[0013] In order to suppress power consumption of the portableinformation terminal, it has been desired to suppress power consumptionof the light emitting device to be employed as the display section.

[0014] Moreover, digitalization of a receiver or a VTR to be used inhome as well as various equipment to be used in a TV or radio broadcaststation has now proceeded. As the next step following digitalization ofa broadcast system is digitalization of broadcast electric waves, i.e.,realization of digital broadcasting. Vigorous research and developmentactivities have been performed toward such a goal.

[0015] One scheme to be used for realizing a digital driving of thelight emitting device is a temporal gradation display. Morespecifically, the temporal gradation display refers to a driving methodin which the gradation display is performed by controlling a time periodduring which the light emitting element is to emit light in one frameperiod.

[0016] In the case where the light emitting device is digitally drivento perform the temporal gradation display, the required number ofrewriting a digital video signal containing image information to beinput to pixels is increased, as the number of gradation of an image tobe displayed is increased. Consequently, power consumption of a group ofdriver circuits to be used for inputting the digital video signal intothe pixels is increased, thereby resulting in increased powerconsumption of the light emitting device.

[0017] In addition, since the light emitting element is of theself-emission type, a time period during which the light emittingelement is to emit light in one frame period varies depending on animage to be displayed. Accordingly, power consumption of the lightemitting device in turn varies depending on an image to be displayed.

[0018] Furthermore, the magnitude of a current to flow through the lightemitting element varies also depending on temperature. Even with avoltage of the same magnitude being applied across the electrodes of thelight emitting element, the magnitude of a current to flow through thelight emitting element varies due to temperature characteristics of thelight emitting element. For example, as the temperature of the organiccompound layer increases, a larger current tends to flow. Accordingly,as an environmental temperature under which the light emitting elementis to be used increases, power consumption of the light emitting deviceincreases, which in turn increases the brightness of the light emittingelement.

[0019] In view of the above-described situations, the present inventionis intended to suppress power consumption of a light emitting device andan electronic apparatus employing the light emitting device as itsdisplay section.

SUMMARY OF THE INVENTION

[0020] A first structure according to the present invention ischaracterized in which in the case where a monochrome display isperformed in a light emitting device, the contrast of an image isdetermined whether to be inverted or not in accordance with what kind ofan image to be displayed by pixels in a pixel portion.

[0021] In accordance with the above-mentioned structure, the magnitudeof a current to flow through the light emitting element can besuppressed to some degree, thereby resulting in a reduced powerconsumption of the light emitting device.

[0022] Furthermore, a second structure in accordance with the presentinvention is characterized in that in a light emitting device thatperforms a digitally-driven time-divisional gradation display, a digitalvideo signal input to a source signal line driver circuit included inthe light emitting device is input into a pixel portion after its numberof bits is reduced. More specifically, a bit of the digital video signalis sequentially cut off from the least significant bit to reduce thenumber of bits of the digital video signal to be input into the pixelportion.

[0023] In accordance with the above-mentioned structure, since thenumber of bits of the digital video signal to be input into the pixelsis reduced, the required number of writing the digital video signal bythe source signal line driver circuit and a gate signal line drivercircuit can be reduced. Thus, power consumption of the source signalline driver circuit and the gate signal line driver circuit can bereduced, thereby resulting in a reduced power consumption of the lightemitting device.

[0024] Moreover, in accordance with a third structure of the presentinvention, a light emitting device is provided with a light emittingelement for monitoring a temperature. One of electrodes of thetemperature-monitoring light emitting element is connected to a constantcurrent source. Thus, by means of temperature characteristics of thetemperature-monitoring light emitting element, the magnitude of acurrent to flow through a light emitting element of a pixel ismaintained at a constant level.

[0025] In accordance with the above-described structure, the magnitudeof a current to flow through the light emitting element of a pixel ismaintained at a constant level, even when a temperature of the organiccompound layer changes. Thus, power consumption of the light emittingdevice can be prevented from increasing even when an environmentaltemperature of the light emitting device increases, which in turn canmaintain the brightness at a constant level.

[0026] In accordance with the first, second, and third structures of thepresent invention as described in the above, it is possible to suppressthe power consumption of a light emitting device and an electronicapparatus which employs the light emitting device. It should be notedthat only either one of the first through third structures is requiredto be included in the present invention, although two or all of thefirst through third structures may be included.

[0027] Structures in accordance with the present invention will befurther described below.

[0028] The present invention provides a display device having aplurality of pixels, wherein a polarity of a digital video signal to beinput into the plurality of pixels is inverted, thereby resulting inbrightness of the plurality of pixels being changed.

[0029] The present invention provides a display device having a pixelportion including a plurality of pixels, and a source signal line drivercircuit, wherein the source signal line driver circuit includes aswitching circuit for switching a polarity of an output, and a polarityof a digital video signal input to the switching circuit is inverted bymeans of a shift signal to be input into the switching circuit and theresultant signal is then input into the plurality of pixels.

[0030] The present invention provides a display device having a pixelportion including a plurality of pixels, and a source signal line drivercircuit, wherein each of the plurality of pixels has a light emittingelement, and the source signal line driver circuit includes a shiftregister, one or more latches and a switching circuit, and a polarity ofa digital video signal input from the one or more latches into theswitching circuit is inverted by means of a shift signal to be inputinto the switching circuit and the resultant signal is then input intothe plurality of pixels.

[0031] The present invention provides a display device having a pixelportion including a plurality of pixels, and a source signal line drivercircuit, wherein each of the plurality of pixels has a light emittingelement, and the source signal line driver circuit includes a shiftregister, one or more latches and a switching circuit, and a polarity ofa digital video signal input from the one or more latches into theswitching circuit is inverted by means of a shift signal to be inputinto the switching circuit and the resultant signal is then input intothe plurality of pixels, and an average of a time period during whichall of the light emitting elements emit light in one frame period isequal to or less than a half of the maximum value of the time periodduring which all of the light emitting elements emit light in one frameperiod.

[0032] The above structures may be characterized in which the switchingcircuit includes an inverter, a first analog switch, and a second analogswitch, wherein the digital video signal input into the switchingcircuit is input into an input terminal of the first analog switch viathe inverter, the digital video signal output from the one or morelatches is input into an input terminal of the second analog switch, theshift signal is input from a first control input terminal of the firstanalog switch and a second control input terminal of the second analogswitch, a signal obtained by inverting the polarity of the shift signalis input from a second control input terminal of the first analog switchand a second control input terminal of the first analog switch, andsignals output from output terminals of the first analog switch and thesecond analog switch are output from the switching circuit.

[0033] The above structures may be characterized in which the switchingcircuit includes an inverter, a first NAND, a second NAND, and a thirdNOR, wherein the first NAND is supplied with the digital video signalvia the inverter and the shift signal, the second NAND is supplied withthe digital video signal and a signal obtained by inverting a polarityof the shift signal, a signal output from the first NAND and a signaloutput from the second NAND are input into the third NOR, and a signaloutput from the third NOR is output from the switching circuit.

[0034] The present invention provides a display device having aplurality of pixels and a source signal line driver circuit, whereinamong a digital video signal to be input into the source signal linedriver circuit, only more significant bits are input into the pluralityof pixels.

[0035] The present invention provides a display device having a pixelportion including a plurality of pixels, and a source signal line drivercircuit, wherein the source signal line driver circuit includes a shiftregister, a first latch, a second latch, and a clock signal controlcircuit, a clock signal is input into the shift register via the clocksignal control circuit to thereby output a timing signal from the shiftregister, a digital video signal is input into and held at the firstlatch by the timing signal, the digital video signal held at the firstlatch is input into and held at the second latch by a latch signal, thedigital video signal input into and held at the second latch is inputinto the plurality of pixels, and the clock signal control circuitreduces the number of bits of the digital video signal to be input intoand held at the first latch by supplying a constant fixed electricalpotential instead of the clock signal to the shift register for aconstant period of time.

[0036] The above structure may be characterized in which the clocksignal control circuit includes a NAND and an inverter, wherein a clocksignal and a selection signal are input into the NAND, and a signaloutput from the NAND is output from the clock signal control circuit viathe inverter.

[0037] The above structure may be characterized in which the clocksignal control circuit includes a first analog switch, a second analogswitch, and an inverter, wherein a selection signal is input via theinverter into a second control input terminal of the first analog switchand a first control input terminal of the second analog switch, theselection signal is input into a first control input terminal of thefirst analog switch and a second control input terminal of the secondanalog switch, a clock signal is input into an input terminal of thefirst analog switch, a fixed electrical potential is supplied to aninput terminal of the second analog switch, and signals output fromoutput terminals of the first analog switch and the second analog switchare output from the clock signal control circuit.

[0038] The present invention provides a display device having a pixelportion including a plurality of pixels, and a source signal line drivercircuit, wherein the source signal line driver circuit includes a shiftregister, a first latch, a second latch, and a timing signal controlcircuit, a timing signal output from the shift register is input intothe first latch via the timing signal control circuit, a digital videosignal is input into and held at the first latch by the timing signalinput into the first latch, the digital video signal held at the firstlatch is input into and held at the second latch by a latch signal, thedigital video signal input into and held at the second latch is inputinto the plurality of pixels, and the timing signal control circuitreduces the number of bits of the digital video signal to be input intoand held at the first latch by supplying to the first latch a constantfixed electrical potential instead of the timing signal output from theshift register for a constant period of time.

[0039] The above structure may be characterized in which the timingsignal control circuit includes a NAND and an inverter, wherein a timingsignal and a selection signal are input into the NAND, and a signaloutput from the NAND is output from the timing signal control circuitvia the inverter.

[0040] The above structure may be characterized in which the timingsignal control circuit includes a first analog switch, a second analogswitch, and an inverter, wherein a selection signal is input via theinverter into a second control input terminal of the first analog switchand a first control input terminal of the second analog switch, theselection signal is input into a first control input terminal of thefirst analog switch and a second control input terminal of the secondanalog switch, the timing signal is input into an input terminal of thefirst analog switch, a fixed electrical potential is supplied to aninput terminal of the second analog switch, and signals output fromoutput terminals of the first analog switch and the second analog switchare output from the timing signal control circuit.

[0041] The present invention provides a display device having a pixelportion including a plurality of pixels and a source signal line drivercircuit, wherein the source signal line driver circuit includes a shiftregister, a first latch, a second latch, and a start pulse signalcontrol circuit, a start pulse signal is input into the shift registervia the start pulse signal control circuit to thereby output a timingsignal from the shift register, a digital video signal is input into andheld at the first latch by the timing signal, the digital video signalheld at the first latch is input into and held at the second latch by alatch signal, the digital video signal input into and held at the secondlatch is input into the plurality of pixels, and the start pulse signalcontrol circuit reduces the number of bits of the digital video signalto be input into and held at the first latch by supplying to the shiftregister a constant fixed electrical potential instead of the startpulse for a constant period of time.

[0042] The above structure may be characterized in which the start pulsesignal control circuit includes a NAND and an inverter, wherein a startpulse signal and a selection signal are input into the NAND, and asignal output from the NAND is output from the start pulse signalcontrol circuit via the inverter.

[0043] The above structure may be characterized in which the start pulsesignal control circuit includes a first analog switch, a second analogswitch, and an inverter, wherein a selection signal is input via theinverter into a second control input terminal of the first analog switchand a first control input terminal of the second analog switch, theselection signal is input into a first control input terminal of thefirst analog switch and a second control input terminal of the secondanalog switch, a start pulse signal is input into an input terminal ofthe first analog switch, a fixed electrical potential is supplied to aninput terminal of the second analog switch, and signals output fromoutput terminals of the first analog switch and the second analog switchare output from the start pulse signal control circuit.

[0044] The present invention provides a display device including aplurality of pixels having a plurality of light emitting elements, and amonitoring light emitting element, wherein the magnitude of a current toflow through the plurality of light emitting elements is maintained bymeans of temperature characteristics of the monitoring light emittingelement.

[0045] The present invention provides a display device including a pixelportion including a plurality of pixels, a buffer amplifier, amonitoring light emitting element, and a constant current source,wherein each of the plurality of pixels includes a thin film transistorand a light emitting element, each of the monitoring light emittingelement and the light emitting element includes a first electrode, asecond electrode, and an organic compound layer disposed between thefirst electrode and the second electrode, the first electrode of themonitoring light emitting element is connected to the constant currentsource, the first electrode of the monitoring light emitting element isalso connected to a non-inverted input terminal of the buffer amplifier,and an output terminal of the buffer amplifier is connected to the firstelectrode of said light emitting element.

[0046] The present invention provides a display device including a pixelportion having a plurality of pixels, a buffer amplifier, a monitoringlight emitting element, a constant current source, and an addingcircuit, wherein each of the plurality of pixels includes a thin filmtransistor and a light emitting element, each of the monitoring lightemitting element and the light emitting element includes a firstelectrode, a second electrode, and an organic compound layer disposedbetween the first electrode and the second electrode, the firstelectrode of the monitoring light emitting element is connected to theconstant current source, the first electrode of the monitoring lightemitting element is also connected to a non-inverted input terminal ofthe buffer amplifier, an output terminal of the buffer amplifier isconnected to an input terminal of the adding circuit, an output terminalof the adding circuit is connected to the first electrode of said lightemitting element, and a constant potential difference is alwaysmaintained between the input terminal and the output terminal of theadding circuit.

[0047] The present invention may be embodied in the form of a videocamera, an image reproduction apparatus, a head mount display, aportable telephone, or a portable information terminal employing theabove-mentioned display device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0048]FIG. 1 is a block diagram of a light emitting device in accordancewith the present invention.

[0049]FIG. 2 is a block diagram of a light emitting device in accordancewith the present invention.

[0050]FIG. 3 is a block diagram of a light emitting device in accordancewith the present invention.

[0051]FIG. 4 is a block diagram of a light emitting device in accordancewith the present invention.

[0052]FIG. 5 is a diagram for illustrating connection of a monitoringlight emitting element of a light emitting device in accordance with thepresent invention.

[0053]FIG. 6 is a diagram for illustrating a pixel portion of a lightemitting device in accordance with the present invention.

[0054]FIG. 7 is an expanded diagram of a pixel of a light emittingdevice in accordance with the present invention.

[0055]FIG. 8 is a diagram for illustrating a driving method of a lightemitting device in accordance with the present invention.

[0056]FIG. 9 is a block diagram of a light emitting device in accordancewith the present invention.

[0057]FIG. 10 is a diagram for illustrating a pixel portion of a lightemitting device in accordance with the present invention.

[0058]FIG. 11 is an expanded diagram of a pixel of a light emittingdevice in accordance with the present invention.

[0059]FIG. 12 is a diagram for illustrating a driving method of a lightemitting device in accordance with the present invention.

[0060]FIG. 13 is a circuit diagram of a source signal line drivercircuit of a light emitting device in accordance with the presentinvention.

[0061]FIG. 14 is a partial plan view of a latch (A).

[0062]FIGS. 15A and 15B are circuit diagrams of a switching circuit.

[0063]FIG. 16 is an equivalent circuit diagram of an analog switch.

[0064]FIG. 17 is a circuit diagram of a source signal line drivercircuit of a light emitting device in accordance with the presentinvention.

[0065]FIGS. 18A and 18B are circuit diagrams of a clock signal controlcircuit, a timing signal control circuit, and a start pulse signalcontrol circuit.

[0066]FIG. 19 is a circuit diagram of a source signal line drivercircuit of a light emitting device in accordance with the presentinvention.

[0067]FIG. 20 is a circuit diagram of a source signal line drivercircuit of a light emitting device in accordance with the presentinvention.

[0068]FIG. 21 is a diagram for illustrating connection of a monitoringlight emitting element of a light emitting device in accordance with thepresent invention.

[0069]FIG. 22 is a circuit diagram of an adding circuit.

[0070]FIGS. 23A through 23D are cross-sectional views for illustratingvarious steps of a fabricating method of a light emitting device.

[0071]FIGS. 24A through 24C are cross-sectional views for illustratingvarious steps of a fabricating method of a light emitting device.

[0072]FIGS. 25A through 25C are cross-sectional views for illustratingvarious steps of a fabricating method of a light emitting device.

[0073]FIGS. 26A and 26B are cross-sectional views for illustratingvarious steps of a fabricating method of a light emitting device.

[0074]FIGS. 27A and 27B are diagram for illustrating electronicapparatuses each employing a light emitting device in accordance withthe present invention.

[0075]FIGS. 28A through 28F are diagram for illustrating electronicapparatuses each employing a light emitting device in accordance withthe present invention.

[0076]FIGS. 29A and 29B show a connection of a light emitting elementfor a monitor of the light emitting device of the present invention, anda characteristic in measurement values of brightness due to temperaturesof the light emitting element, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment Mode 1

[0077] A first structure in accordance with the present invention willbe now described. FIG. 1 shows a block diagram of a light emittingdevice having the first structure in accordance with the presentinvention.

[0078] Reference numeral 101 denotes a pixel portion in which aplurality of pixels are provided in matrix. Reference numerals 102 and103 denote a source signal line driver circuit and a gate signal linedriver circuit, respectively.

[0079] The source signal line driver circuit 102 includes a shiftregister 102-1, a latch (A) 102-2, a latch (B) 102-3, and a switchingcircuit 102-4. It should be noted that the source signal line drivercircuit of the present invention may further include a level shift, abuffer or the like, in addition to the components mentioned above.

[0080] Although not illustrated, the gate signal line driver circuit 103includes a shift register and a buffer. In some cases, the gate signalline driver circuit 103 may further include a level shift in addition tothe shift register and the buffer. Gate electrodes of pixel TFTs in onerow are connected to one gate signal line, and therefore, all of thepixels TFTs in one row have to be simultaneously turned on. Accordingly,a buffer capable of allowing a large current to flow therethrough isused.

[0081] In the source signal line driver circuit 102, a clock signal(CLK) and a start pulse (SP) are input into the shift register 102-1.The shift register 102-1 sequentially generates a timing signal based onthese clock signal (CLK) and start pulse (SP) and supplies the generatedtiming signal sequentially to a circuit in the succeeding stage.

[0082] The timing signal to be output from the shift register 102-1 maybe sequentially supplied to the circuit in the succeeding stage througha buffer or the like (not illustrated). The timing signal from the shiftregister 102-1 is buffered and amplified by the buffer or the like.Since a number of circuits or elements are connected to a wiring towhich the timing signal is to be supplied, a large load capacitance(parasitic capacitance) exists. In order to prevent a rising edge or atrailing edge of the timing signal from being rounded due to such alarge load capacitance, the above-mentioned buffer is provided.

[0083] The timing signal output from the shift register 102-1 issupplied to the latch (A) 102-2. The latch (A) 102-2 includes latches inmultiple stages for processing an n-bit digital video signal. When thetiming signal is input to the latch (A) 102-2, it sequentially takes inthe n-bit digital video signal to be externally supplied to the sourcesignal line driver circuit 102 and held them therein.

[0084] When the digital video signal is taken in into the latch (A)102-2, the digital video signal may be sequentially input into thelatches in the multiple stages included in the latch (A) 102-2. However,the present invention is not limited to such a structure. A so-calleddivision driving may be performed in which the latches in the multiplestages included in the latch (A) 102-2 are divided into several groupsand the digital video signal is input every group in parallel andsimultaneously. In such a case, the number of the groups is referred toas the division number. For example, in the case where the latches aredivided into four groups, it can be said that the device is driventhrough the quarter-division scheme.

[0085] A time period required for completing all of the writing of thedigital video signal into the latches in all of the stages of the latch(A) 102-2 is referred to as a line period. More specifically, the lineperiod refers to a time period measured from a timing when the writingof the digital video signal into the latch in the leftmost stage in thelatch (A) 102-2 starts until a timing when the writing of the digitalvideo signal into the latch in the rightmost stage ends. In practice,the line period may include a horizontal blanking period in addition tothe above-described line period.

[0086] After the one line period ends, latch signals are supplied to thelatch (B) 102-3. At this moment, the digital video signal that has beenwritten into and held at the latch (A) 102-2 is simultaneously sent outto the latch (B) 102-3 to be written into latches in all of the stagesof the latch (B) 102-3 and held therein.

[0087] Further digital video signal to be externally supplied to thesource signal line driver circuit 102 is again sequentially written,based on the timing signal from the shift register 102-1, into the latch(A) 102-2 from which the previous digital video signal was sent out tothe latch (B) 102-3.

[0088] During the second turn of the one line period, the digital videosignal that has been written into and held at the latch (B) 102-3 issimultaneously sent out to the switching circuit 102-4. The switchingcircuit 102-4 causes the polarity of the digital video signal input fromthe latch (B) 102-2 to be inverted, or alternatively allows the polarityof those digital video signal not to be inverted, in accordance withshift signals, and outputs the resultant signals.

[0089] The digital video signal includes information of either “0” or“1”. The digital video signal corresponding to “0” is a signal having aHi potential, while the digital video signal corresponding to “1” is asignal having a Lo potential, or vice versa. The inversion of thepolarity of the digital video signal means that the digital video signalhaving information of “0” is converted into that having information of“1”, while the digital video signal having information of “1” isconverted into that having information of “0”.

[0090] The shift signal is a signal to be used for selecting whether thepolarity of the digital video signal input from the latch (B) 102-2 isto be inverted or not. The polarity of the digital video signal isinverted by the shift signal when an average of a time period duringwhich all of the light emitting elements emit light in one frame periodbecomes longer than a half of a time period during which the lightemitting elements emit light in one frame period in the case where thetotally white is to be displayed in the pixel portion 101, therebyresulting in power consumption being reduced. On the other hand, when anaverage of the time period during which all of the light emittingelements emit light in one frame period becomes shorter than a half ofthe time period during which the light emitting elements emit light inone frame period in the case where the totally white is to be displayedin the pixel portion 101, the polarity of the digital video signal isnot allowed to be inverted in accordance with the shift signal, for thepurpose of suppressing the power consumption.

[0091] Whether the polarity of the digital video signal should beinverted or not in accordance with the shift signal may be chosen by auser, or alternatively, may be automatically chosen based on an image tobe displayed.

[0092] The digital video signal output from the switching circuit 102-4is input into the source signal lines.

[0093] On the other hand, in the gate signal line driver circuit 103, agate signal from a shift register (not illustrated) is input into abuffer (not illustrated), and further input into a corresponding gatesignal line (also referred to as a scanning line).

[0094] In accordance with the gate signal input into the gate signalline, the digital video signal input into the source signal lines isinput into the pixels.

[0095] In the above description, the source signal line driver circuit102 and the gate signal line driver circuit 103 may be provided on thesame substrate as the pixel portion 101. Alternatively, those drivercircuits 102 and 103 may be provided on an IC chip and connected to thepixel portion 101 via some techniques such as FPC or TAB.

[0096] In accordance with the above-mentioned structure of the presentembodiment of the invention, in the case where the light emitting devicefor performing a digitally-driven time-divisional gradation displaydisplays a monochrome image, the contrast of an image can be invertedbased on natures of the image to be displayed in the pixel portion. Morespecifically, the contrast of the image to be displayed in the pixelportion is inverted when an average of a time period during which all ofthe light emitting elements emit light in one frame period becomeslonger than a half of a time period during which the light emittingelements emit light in one frame period in the case where the totallywhite is to be displayed in the pixel portion 101. On the other hand,when an average of the time period during which all of the lightemitting elements emit light in one frame period becomes shorter than ahalf of the time period during which the light emitting elements emitlight in one frame period in the case where the totally white is to bedisplayed in the pixel portion 101, it is desirable that the contrast ofthe image to be displayed in the pixel portion is not allowed to beinverted.

[0097] In the above description of the present embodiment, the switchingcircuit is included in the source signal line driver circuit.Alternatively, it is acceptable that the switching circuit is notincluded in the source signal line driver circuit.

[0098] In the present embodiment mode, only the situation where thedigital video signal is employed has been described. Alternatively, thepresent invention may be applied to the case where an analog videosignal is used instead of the digital video signal.

[0099] Accordingly, the magnitude of a current to flow through the lightemitting element can be suppressed to some extent in accordance with thefirst structure of the present invention, thereby resulting in the powerconsumption of the resultant light emitting device being suppressed.

Embodiment Mode 2

[0100] A second structure in accordance with the present invention willbe now described. FIG. 2 shows a block diagram of a light emittingdevice having the second structure in accordance with the presentinvention. In FIG. 2, the same components as shown in FIG. 1 aredesignated with the same reference numerals.

[0101] The light emitting device in the present embodiment mode employsa clock signal control circuit 106 which allows a constant electricalpotential instead of the clock signal (CLK) to be applied to the shiftregister 102-1.

[0102] More specifically, the light emitting device is configured toinput a constant electrical potential (fixed electrical potential) intothe shift register 102-1, instead of the clock signal, for a constanttime period by means of the clock signal control circuit 106. The abovestructure prevents the timing signal that is to be used for inputtingthe digital video signal at less significant bits in the range from thefirst bit to the m-th bit (m is any integer in the range from 1 to n)into the latch (A) 102-2 from being input into the latch (A) 102-2.Accordingly, only the digital video signal at more significant bits inthe range from the (m+1)-th bit to the n-th bit can be written into thelatch (A) 102-2.

[0103] The light emitting device in the present embodiment mode isdifferent from that shown in FIG. 1 in that the source signal linedriver circuit 102 does not include the switching circuit 102-4.Accordingly, the digital video signal that has been written into andheld at the latch (B) 102-3 is input into the source signal lines bymeans of the latch signal to be input into the latch (B) 102-3.

[0104] In accordance with the present embodiment mode, in the lightemitting device that performs a digitally-driven time-divisionalgradation display, the digital video signal input into the source signalline driver circuit contained in the light emitting device is input intothe pixel portion after the number of bits thereof is reduced. Morespecifically, the number of bits of the digital video signal to be inputinto the pixel portion is reduced by sequentially cutting off a bit ofthe digital video signal from the least significant bit.

[0105] In accordance with the above-described structure, the number ofbits of the digital video signal to be input into the pixel portion isreduced, and therefore, the required number of writing the digital videosignal into the pixels by means of the source signal line driver circuitand the gate signal line driver circuit can be reduced. Thus, the powerconsumption of the source signal line driver circuit and the gate signalline driver circuit can be suppressed, thereby resulting in the powerconsumption of the light emitting device being suppressed.

[0106] It should be noted that in the present embodiment mode, the clocksignal control circuit 106 may be provided on the same substrate as thepixel portion 101, or alternatively, may be formed in an IC chip.

Embodiment Mode 3

[0107] Another example of the second structure in accordance with thepresent invention, which is different from the one described inEmbodiment Mode 2, will be now described. FIG. 3 shows a block diagramof a light emitting device having the second structure in accordancewith the present invention. In FIG. 3, the same components as shown inFIG. 1 are designated with the same reference numerals.

[0108] The light emitting device in the present embodiment mode employsa timing signal control circuit 107 which allows a constant electricalpotential, instead of the timing signal output from the shift register102-1, to be applied to the latch (A) 102-2.

[0109] More specifically, the light emitting device is configured toinput a constant electrical potential (fixed electrical potential) intothe latch (A) 102-2, instead of the timing signal output from the shiftregister 102-1, for a constant time period by means of the timing signalcontrol circuit 107. The above structure prevents the timing signal thatis to be used for inputting the digital video signal at less significantbits in the range from the first bit to the m-th bit (m is any integerin the range from 1 to n) into the latch (A) 102-2 from being input intothe latch (A) 102-2. Accordingly, only the digital video signal at moresignificant bits in the range from the (m+1)-th bit to the n-th bit canbe written into the latch (A) 102-2.

[0110] It should be noted that in the present embodiment mode, the fixedelectrical potential is required to be at such a level that prevents thedigital video signal from being written into the latch (A) 102-2.

[0111] In accordance with the present embodiment mode, in the lightemitting device that performs a digitally-driven time-divisionalgradation display, the digital video signal input into the source signalline driver circuit contained in the light emitting device is input intothe pixel portion after the number of bits thereof is reduced. Morespecifically, the number of bits of the digital video signal to be inputinto the pixel portion is reduced by sequentially cutting off the bit ofthe digital video signal from the least significant bit.

[0112] In accordance with the above-described structure, the number ofbits of the digital video signal to be input into the pixel portion isreduced, and therefore, the required number of writing the digital videosignal into the pixels by means of the source signal line driver circuitand the gate signal line driver circuit can be reduced. Thus, the powerconsumption of the source signal line driver circuit and the gate signalline driver circuit can be suppressed, thereby resulting in the powerconsumption of the light emitting device being suppressed.

[0113] It should be noted that in the present embodiment mode, thetiming signal control circuit 107 may be provided on the same substrateas the pixel portion 101, or alternatively, may be formed in an IC chip.

Embodiment Mode 4

[0114] Still another example of the second structure in accordance withthe present invention, which is different from the ones described inEmbodiment Modes 2 and 3, will be now described. FIG. 4 shows a blockdiagram of a light emitting device having the second structure inaccordance with the present invention. In FIG. 4, the same components asshown in FIG. 1 are designated with the same reference numerals.

[0115] The light emitting device in the present embodiment mode employsa start pulse signal control circuit 108 which allows a constantelectrical potential, instead of the start pulse signal (SP), to beapplied to the shift register 102-1.

[0116] More specifically, the light emitting device is configured toinput a constant electrical potential (fixed electrical potential) intothe shift register 102-1, instead of the start pulse signal, for aconstant time period by means of the start pulse signal control circuit108, so that the timing signal that is to be used for inputting thedigital video signal at less significant bits in the range from thefirst bit to the m-th bit (m is any integer in the range from 1 to n)into the latch (A) 102-2 is prevented from being input into the latch(A) 102-2. Accordingly, only the digital video signal at moresignificant bits in the range from the (m+1)-th bit to the n-th bit canbe written into the latch (A) 102-2.

[0117] It should be noted that in the present embodiment mode, the fixedelectrical potential is required to be at such a level that prevents thetiming signal from being output from the shift register 102-1.

[0118] In accordance with the present embodiment mode, in the lightemitting device that performs a digitally-driven time-divisionalgradation display, the digital video signal input into the source signalline driver circuit contained in the light emitting device is input intothe pixel portion after the number of bits thereof is reduced. Morespecifically, the number of bits of the digital video signal to be inputinto the pixel portion is reduced by sequentially cutting off the bit ofthe digital video signal from the least significant bit.

[0119] In accordance with the above-described structure, the number ofbits of the digital video signal to be input into the pixel portion isreduced, and therefore, the required number of writing the digital videosignal into the pixels by means of the source signal line driver circuitand the gate signal line driver circuit can be reduced. Thus, the powerconsumption of the source signal line driver circuit and the gate signalline driver circuit can be suppressed, thereby resulting in the powerconsumption of the light emitting device being suppressed.

[0120] It should be noted that in the present embodiment mode, the startpulse signal control circuit 108 may be provided on the same substrateas the pixel portion 101, or alternatively, may be formed in an IC chip.

Embodiment Mode 5

[0121] A third structure in accordance with the present invention willbe now described with reference to FIG. 5.

[0122] Reference numeral 502 denotes a buffer amplifier, referencenumeral 503 denotes a monitoring light emitting element, and referencenumeral 504 denotes a constant current source. One of electrodes of themonitoring light emitting element 503 is connected to the constantcurrent source 504, so that a constant current always flows through themonitoring light emitting element 503. When a temperature of an organiccompound layer contained in the light emitting element changes, themagnitude of the current to flow through the monitoring light emittingelement 503 does not change, but rather, an electrical potential of theelectrode of the monitoring light emitting element 503 connected to theconstant current source 504 changes.

[0123] On the other hand, the buffer amplifier 502 includes two inputterminals and one output terminal. One of the two input terminals is anon-inverted input terminal (+), while the other is an inverted inputterminal (−). An electrical potential at one of electrodes of themonitoring light emitting element 503 is supplied to the bufferamplifier 502.

[0124] An output terminal of the buffer amplifier 502 is connected tothe inverted input terminal (−), and a potential of the output terminalis applied to a pixel electrode in a pixel portion of the light emittingelement.

[0125] The buffer amplifier 502 is a circuit for preventing anelectrical potential at a pixel electrode of the monitoring lightemitting element 503 connected to the constant current source 504changes in accordance with a load such as a wiring capacitance or thelike. Accordingly, the electrical potential provided to the non-invertedinput terminal of the buffer amplifier 502 is output from an outputterminal to be supplied to the power source line as the power sourcepotential, without being changed in accordance with a load such as awiring capacitance or the like.

[0126] Accordingly, even when a temperature of the monitoring lightemitting element 503 or the organic compound layer of the light emittingelement in the pixel portion changes due to a change in an environmentaltemperature, the power source potential is changed so as to allow aconstant current to flow through the light emitting element. Thus, evenwhen the environmental temperature of the light emitting deviceincreases, power consumption of the light emitting device can beprevented from increasing.

[0127] In the present embodiment mode, the buffer amplifier 502, themonitoring light emitting element 503, and the constant current source504 may be provided on the same substrate as the pixel portion, oralternatively, may be formed in an IC chip. Moreover, the monitoringlight emitting element 503 may be included in the pixel portion, oralternatively, may be provided independently of the pixel portion.

[0128] The present invention can suppress power consumption of a lightemitting device and an electronic apparatus employing the light emittingdevice in accordance with the above-described first through thirdstructures. It should be noted that only either one of the first throughthird structures is required to be included in the present invention,although two or all of the first through third structures may beincluded.

[0129] The present invention can allow power consumption of the lightemitting device to be suppressed by means of the above-described threestructures.

Embodiments

[0130] Several embodiments will be described below.

Embodiment 1

[0131] In the present embodiment, the structure of a pixel portion of alight emitting device and its driving method in accordance with thepresent invention will be described.

[0132]FIG. 6 shows an expanded view of the pixel portion 301 of thelight emitting device in accordance with the present embodiment of theinvention. Source signal lines (S1 to Sx), power source lines (V1 toVx), and gate signal lines (G1 to Gy) are provided in the pixel portion301.

[0133] In the present embodiment, a pixel 304 refers to a region inwhich one of the source signal lines (S1 to Sx), one of the power sourcelines (V1 to Vx), and one of the gate signal lines (G1 to Gy) areprovided. In the pixel portion 301, a plurality of the pixels 304 arearranged in matrix.

[0134] An expanded view of the pixel 304 is shown in FIG. 7. In FIG. 7,reference numeral 305 denotes a switching TFT. A gate electrode of theswitching TFT 305 is connected to the gate signal line G (G1 to Gx). Oneof a source region and a drain region of the switching TFT 305 isconnected to the source signal line S (S1 to Sx), while the otherthereof is connected to a gate electrode 306 of a current-controllingTFT 306 as well as to a capacitor 308 of each pixels.

[0135] The capacitor 308 is provided for holding a gate potential of thecurrent-controlling TFT 306 (an electrical potential difference betweenthe gate electrode and the source region) when the switching TFT 305 isin the non-selected condition (off condition). Although the capacitor308 is provided in the present embodiment, the present invention is notlimited to such a structure. The capacitor 308 may be omitted.

[0136] One of the source region and the drain region of thecurrent-controlling TFT 306 is connected to the power source line V (V1to Vx), while the other is connected to the light emitting element 307.The power source line V is connected to the capacitor 308.

[0137] The light emitting element 307 is composed of an anode, acathode, and an organic compound layer provided between the anode andthe cathode. In the case where the anode is connected to the sourceregion or the drain region of the current-controlling TFT 306, the anodefunctions as the pixel electrode and the cathode functions as a counterelectrode. On the other hand, in the case where the cathode is connectedto the source region or the drain region of the current-controlling TFT306, the cathode functions as the pixel electrode and the anodefunctions as the counter electrode.

[0138] A counter potential is supplied to the counter electrode of thelight emitting element 307. In addition, the power source potential issupplied to the power source line V. The power source potential and thecounter potential are supplied to the light emitting device of thepresent invention by means of a power source provided by anexternally-attached IC chip or the like.

[0139] The switching TFT 305 and the current-controlling TFT 306 may beeither of the n-channel type TFT or the p-channel type TFT. It should benoted, however, that in the case where the source region or the drainregion of the current-controlling TFT 306 is connected to the anode ofthe light emitting element 307, it is preferable that thecurrent-controlling TFT 306 is the p-channel type TFT. On the otherhand, in the case where the source region or the drain region of thecurrent-controlling TFT 306 is connected to the cathode of the lightemitting element 307, it is preferable that the current-controlling TFT306 is the n-channel type TFT.

[0140] The switching TFT 305 and the current-controlling TFT 306 mayhave a multi-gate structure such as a double gate structure, a triplegate structure or the like, rather than a single gate structure.

[0141] Then, a driving method of the light emitting device of thepresent invention that includes the above-mentioned structure will bedescribed with reference to FIG. 8.

[0142] First, the power source potential of the power source linebecomes to be equal to an electrical potential of the counter electrodeof the light emitting element. Then, a gate signal is input from thegate signal line driver circuit to the gate signal line G1. As a result,the switching TFTs 305 of all of the pixels connected to the gate signalline G1 (i.e., the pixels in the first row) are placed in the ON state.

[0143] Simultaneously, the digital video signal at the first bit isinput from the source signal line driver circuit into the source signallines (S1 to Sx). The digital video signal is input to the gateelectrode of the current-controlling TFT 306 via the switching TFT 305.

[0144] Then, at the same time when the input of the gate signal into theG1 is completed, the similar gate signal is input into the next gatesignal line G2. Thus, the switching TFTs 305 of all of the pixelsconnected to the gate signal line G2 (i.e., the pixels in the secondrow) are placed in the ON state, thereby the digital video signal at thefirst bit is input from the source signal lines (S1 to Sx) into thepixels in the second row.

[0145] Thereafter, the gate signal is sequentially input to all of thegate signal lines (G1 to Gx). A time period required for selecting allof the gate signal lines (G1 to Gx) and inputting the digital videosignal at the first bit into the pixels in all of the rows is a writingperiod Ta1.

[0146] When the writing period Ta1 is completed, a light emitting periodTr1 then starts. During the light emitting period Tr1, the power sourcepotential of the power source line comes to be at such a potential levelthat provides a potential difference with respect to the counterelectrode, so that the light emitting element can emit light when thepower source potential is supplied to the pixel electrode of the lightemitting element.

[0147] In the present embodiment, in the case where the digital videosignal has information of “0”, the current-controlling TFT 306 is in theOFF state. Accordingly, the power source potential is not supplied tothe pixel electrode of the light emitting element 307. As a result, thelight emitting element 307 included in the pixel to which the digitalvideo signal having information of “0” is supplied does not emit light.

[0148] On the other hand, in the case where the digital video signal hasinformation of “1”, the current-controlling TFT 306 is in the ON state.Accordingly, the power source potential is supplied to the pixelelectrode of the light emitting element 307. As a result, the lightemitting element 307 included in the pixel to which the digital videosignal having information of “1” is supplied emits light.

[0149] Thus, during the display period Tr1, the light emitting element307 is placed either in the emission state or the non-emission state, sothat all of the pixels perform a display operation. A time period duringwhich the pixel performs the display operation is referred to as adisplay period Tr. More specifically, the display period that startswhen the digital video signal at the first bit is input into the pixelis referred to as Tr1. In FIG. 8, only the display period of the pixelsin the first row is illustrated for the purpose of simplification of thedescription. Timings at which the respective display periods for all ofthe rows start are the same.

[0150] When the display period Tr1 is completed, a next writing periodTa2 starts, and the power source potential of the power source linecomes to be equal to the electrical potential of the counter electrodeof the light emitting element. Similarly in the case of the writingperiod Ta1, all of the gate signal lines are sequentially selected, andthe digital video signal at the second bit is input into all of thepixels. A time period required for completing the input of the digitalvideo signal at the second bit into the pixels in all of the rows isreferred to as a writing period Ta2.

[0151] When the writing period Ta2 is completed, a display period Tr2then starts, and the power source potential of the power source linecomes to be at such a potential level that provides a potentialdifference with respect to the counter electrode, so that the lightemitting element can emit light when the power source potential issupplied to the pixel electrode of the light emitting element. Thus, allof the pixels perform the display operation.

[0152] The above-described operations are repeated until the digitalvideo signal at the n-th bit is input into the pixels, so that thewriting period Ta and the display period Tr appear alternately. Afterall of the display periods (Tr1 to Trn) are completed, one image can bedisplayed. In the driving method in accordance with the presentinvention, a time period required for displaying one image is referredto as one frame period (F). After a certain one frame period (F) iscompleted, the next one frame period is started. The writing period Ta1again appears, and the above-described operations are repeated.

[0153] In a normal light emitting device, it is preferable to provide 60or more frame periods per one second. If the number of images to bedisplayed in one second is smaller than 60, flickering of the image maybecome visually significant.

[0154] In the present embodiment, it is necessary that the sum of all ofthe writing periods is shorter than one frame period and ratios amongthe respective display periods are set to satisfy the relationship ofTr1:Tr2:Tr3: . . . :Tr(n−1):Trn=2⁰:2¹:2²: . . . :2^((n−2)):2^((n−1)).Through the combination of the display periods, a desired gradationdisplay among the total of 2^(n) gradations can be realized.

[0155] The gradation to be displayed by a particular pixel in a certainone frame period is determined by obtaining the sum of the displayperiods during which the light emitting element emits light in thatframe period. For example, assuming that n=8 and the brightness obtainedwhen the pixel emits light in all of the display periods is expressed as100%, the brightness of 1% can be realized in the case where the pixelemits light in Tr1 and Tr2, while the brightness of 60% can be realizedwhen Tr3, Tr5, and Tr8 are selected.

[0156] The display periods Tr1 through Tm may appear on any order. Forexample, during one frame period, the display periods may be controlledto appear in such an order that Tr1 is followed by Tr3, Tr5, Tr2, . . ..

[0157] Although the level of the power source potential at the powersource line is changed by means of the writing period and the displayperiod in the above description of the present embodiment, the presentinvention is not limited thereto. A potential difference which allowsthe light emitting element to emit light when the power source potentialis supplied to the pixel electrode of the light emitting element may becontrolled to always exist between the power source potential and theelectrical potential at the counter electrode. In such a case, the lightemitting element can emit light even in the writing period. Accordingly,the gradation to be displayed by a particular pixel in a certain frameperiod is determined by the sum of the writing periods and the displayperiods during which the light emitting element emits light in thatframe period. In this case, it is necessary that the sum of the writingperiods and the display periods corresponding to the digital videosignal at the respective bits is set to satisfy the relationship of(Ta1+Tr1):(Ta2+Tr2):(Ta3+Tr3): . . .:(Ta(n−1)+Tr(n−1)):(Tan+Trn)=2⁰:2¹:2²: . . . 2^((n−2)):2^((n−1)).

Embodiment 2

[0158] In the present embodiment, another example of the structure of apixel portion of a light emitting device and its driving method inaccordance with the present invention, different from those in theEmbodiment 1, will be described.

[0159]FIG. 9 shows an exemplary block diagram of a light emitting devicein the present embodiment. The light emitting device in FIG. 9 includesa pixel portion 901 by TFT formed on the substrate and includes a sourcesignal side driver circuit 902, a writing gate signal side drivercircuit (first gate signal line driver circuit) 903 a, and an erasuregate signal line driver circuit (second gate signal line driver circuit)903 b, each provided in the periphery of the pixel portion. Although thelight emitting device with one source signal side driver circuit isdescribed in the present embodiment, two of the source signal sidedriver circuits may be provided.

[0160] The source signal side driver circuit 902 has at least one of thefirst through third structures of the present invention describedpreviously.

[0161] In the present embodiment, the source signal line driver circuit902 and the writing gate signal side driver circuit 903 a and theerasure gate signal line driver circuit 903 b may be provided on thesame substrate as the pixel portion 901, or alternatively, may be formedon an IC chip and connected to the pixel portion 901 via a certainconnector such as FPC, TAB or the like.

[0162] An expanded view of the pixel portion 901 is shown in FIG. 10. InFIG. 10, source signal lines (S1 to Sx), power source lines (V1 to Vx),and writing gate signal lines (first gate signal lines) (Ga1 to Gay),and erasure gate signal lines (second gate signal lines) (Ge1 to Gey)are provided in the pixel portion 901.

[0163] The pixel 904 refers to a region in which one of the sourcesignal lines (S1 to Sx), one of the power source lines (V1 to Vx), oneof the writing gate signal lines (Ga1 to Gay), and one of the erasuregate signal lines (Ge1 to Gey) are provided. In the pixel portion 901, aplurality of the pixels 904 are arranged in matrix.

[0164] An expanded view of the pixel 904 is shown in FIG. 11. In FIG.11, reference numeral 907 denotes the switching TFT. A gate electrode ofthe switching TFT 907 is connected to the gate signal line Ga (Ga1 toGay). One of a source region and a drain region of the switching TFT 907is connected to the source signal line S (S1 to Sx), while the otherthereof is connected to a gate electrode of a current-controlling TFT908 as well as to a capacitor 912 and source and drain regions of anerasure TFT 909 included in each pixels.

[0165] The capacitor 912 is provided for holding a gate potential of thecurrent-controlling TFT 908 when the switching TFT 907 is in thenon-selected condition (off condition). Although the capacitor 912 isprovided in the present embodiment, the present invention is not limitedto such a structure. The capacitor 912 may be omitted.

[0166] One of the source region and the drain region of thecurrent-controlling TFT 908 is connected to the power source line V (V1to Vx), while the other thereof is connected to the light emittingelement 910. The power source line V is connected to the capacitor 912.

[0167] One of the source region and the drain region of the erasure TFT909 that is not connected to the source or drain region of the switchingTFT 907 is connected to the power source line V. A gate electrode of theerasure TFT 909 is connected to the erasure gate signal line Ge.

[0168] The light emitting element 910 is composed of an anode, acathode, and an organic compound layer provided between the anode andthe cathode. In the case where the anode is connected to the sourceregion or the drain region of the current-controlling TFT 908, the anodefunctions as the pixel electrode and the cathode functions as a counterelectrode. On the other hand, in the case where the cathode is connectedto the source region or the drain region of the current-controlling TFT908, the cathode functions as the pixel electrode and the anodefunctions as the counter electrode.

[0169] A counter potential is supplied to the counter electrode 911 ofthe light emitting element 910. In addition, the power source potentialis supplied to the power source line V. A potential difference betweenthe counter potential and the power source potential is alwaysmaintained at such a level that causes the light emitting element toemit light when the power source potential is applied to the pixelelectrode. The power source potential and the counter potential aresupplied to the light emitting device of the present invention by meansof a power source provided by an externally-attached IC chip or thelike.

[0170] In the typical light emitting device to date, when the amount oflight emission per unit light emission area of a pixel is 200 cd/m², acurrent of several mA/cm² per unit area of a pixel portion is requiredto flow. Thus, especially with a larger display area, it becomesdifficult to control the magnitude of the electrical potential to besupplied from the power source provided in the IC chip by means of aswitch. In the present embodiment, the power source potential and thecounter potential are always maintained to be constant, and therefore,the magnitude of the electrical potential to be supplied from the powersource provided in the IC chip is not required to be controlled by meansof a switch. Accordingly, the present embodiment is useful for realizinga panel having a larger display size.

[0171] The switching TFT 907, the current-controlling TFT 908, and theerasure TFT 909 may be either of the n-channel type TFT or the p-channeltype TFT. It should be noted, however, that in the case where the sourceregion or the drain region of the current-controlling TFT 908 isconnected to the anode of the light emitting element 910, it ispreferable that the current-controlling TFT 908 is the p-channel typeTFT. On the other hand, in the case where the source region or the drainregion of the current-controlling TFT 908 is connected to the cathode ofthe light emitting element 910, it is preferable that thecurrent-controlling TFT 908 is the n-channel type TFT.

[0172] The switching TFT 907, the current-controlling TFT 908, and theerasure TFT 909 may have a multi-gate structure such as a double gatestructure, a triple gate structure or the like, rather than a singlegate structure.

[0173] Then, a driving method of the light emitting device of thepresent invention that includes the above-mentioned structure will bedescribed with reference to FIG. 12.

[0174] First, a writing gate signal is input from the writing gatesignal line driver circuit 903 a to the writing gate signal line Ga1,and thus, the switching TFTs 907 of all of the pixels connected to thewriting gate signal line Ga1 (i.e., the pixels in the first row) areplaced in the ON state. In the present specification, when all of theTFTs having a gate electrode connected to a certain signal line, thesignal line is referred to as being selected. Thus, in theabove-described case, the writing gate signal line Ga1 is beingselected.

[0175] Simultaneously, the digital video signal at the first bit isinput from the source signal line driver circuit 902 into the sourcesignal lines (S1 to Sx). More specifically, the digital video signal isinput to the gate electrode of the current-controlling TFT 908 via theswitching TFT 907.

[0176] In the present embodiment, in the case where the digital videosignal has information of “0”, the current-controlling TFT 908 is in theOFF state. Accordingly, the power source potential is not supplied tothe pixel electrode of the light emitting element 910. As a result, thelight emitting element 910 included in the pixel to which the digitalvideo signal having information of “0” is supplied does not emit light.

[0177] On the other hand, in the case where the digital video signal hasinformation of “1”, the current-controlling TFT 908 is in the ON state.Accordingly, the power source potential is supplied to the pixelelectrode of the light emitting element 910. As a result, the lightemitting element 910 included in the pixel to which the digital videosignal having information of “1” is supplied emits light.

[0178] Thus, at the same time when the digital video signal is inputinto the pixels in the first row, the light emitting element is placedeither in the emission state or the non-emission state, so that all ofthe pixels in the first row perform a display operation. A time periodduring which the pixel performs the display operation is referred to asa display period Tr. More specifically, the display period that startswhen the digital video signal at the first bit is input into the pixelis referred to as Tr1. In FIG. 12, only the display period of the pixelsin the first row is illustrated for the purpose of simplification of thedescription. Timings at which the display periods for the respectiverows start are offset from each other by a certain time difference.

[0179] Then, at the same time when the selection of the Ga1 iscompleted, the next writing gate signal line Ga2 is selected by thewriting gate signal. Thus, the switching TFTs 907 of all of the pixelsconnected to the writing gate signal line Ga2 are placed in the ONstate, thereby the digital video signal at the first bit is input fromthe source signal lines (S1 to Sx) into the pixels in the second row.

[0180] Thereafter, all of the writing gate signal lines (Ga1 to Gax) aresequentially selected. A time period required for selecting all of thewriting gate signal lines (Ga1 to Gax) and inputting the digital videosignal at the first bit into the pixels in all of the rows is a writingperiod Ta1.

[0181] On the other hand, before the digital video signal at the firstbit is input into the pixels in all of the rows, in other words, beforethe writing period Ta1 is completed, the erasure gate signal line Gel isselected by an erasure gate signal to be input from the erasure gatesignal line driver circuit 903 b, in parallel to the input of thedigital video signal of the first bit into the pixels.

[0182] When the erasure gate signal line Gel is selected, the erasureTFTs 909 in all of the pixels connected to the erasure gate signal lineGel (the pixels in the first row) are placed in the ON state. Thus, thepower source potential of the power source line (V1 to Vx) is suppliedto the gate electrodes of the current-controlling TFTs 908 in the pixelsin the first row.

[0183] When the power source potential is supplied to the gateelectrodes of the current-controlling TFTs 908, the current-controllingTFTs 908 are placed in the OFF state. Thus, the power source potentialis not supplied to the pixel electrodes of the light emitting elements910, so that all of the light emitting elements included in the pixelsin the first row are placed in the non-emission state. Thus, the pixelsin the first row do not performs a display operation. In other words,the digital video signal that has been held at the gate electrode of thecurrent-controlling TFT since the selection of the writing gate signalline Ga1 is erased when the power source potential is supplied to thegate electrode of the current-controlling TFT. Thus, the pixels in thefirst row do not performs a display operation.

[0184] A time period during which the pixel does not perform a displayoperation is referred to as a non-display period Td. The display periodTr1 for the pixels in the first row is completed simultaneously when theerasure gate signal is input into the erasure gate signal line Ge1, andthe non-display period Td1 starts.

[0185] In FIG. 12, only the non-display period for the pixels in thefirst row is particularly illustrated for the purpose of simplificationof the description. Timings at which the non-display periods for therespective rows start are offset from each other by a certain timedifference.

[0186] Then, at the same time when the selection of the Ge1 iscompleted, the next erasure gate signal line Ge2 is selected by theerasure gate signal. Thus, the erasure TFTs 909 of all of the pixelsconnected to the erasure gate signal line Ge2 (the pixels in the secondrow) are placed in the ON state. The power source potential of the powersource lines (V1 to Vx) is supplied to the gate electrode of thecurrent-controlling TFT 908 via the erasure TFT 909. When the powersource potential is supplied to the gate electrode of thecurrent-controlling TFT 908, the current-controlling TFT 908 is placedin the OFF state. Thus, the power source potential is not supplied tothe pixel electrode of the light emitting element 910, so that all ofthe light emitting elements included in the pixels in the second row areplaced in the non-emission state. Thus, the pixels in the second row donot performs a display operation and are placed in the non-displaystate.

[0187] Then, all of the erasure gate signal lines are sequentiallyselected by the erasure gate signal. A time period required forselecting all of the erasure gate signal lines (Ga1 to Gax) and erasingthe digital video signal at the first bit held in the pixels in all ofthe rows is referred to as the erasure period Te1.

[0188] On the other hand, before the digital video signal at the firstbit held in the pixels in all of the rows is erased, in other words,before the erasure period Te1 is completed, the writing gate signal lineGa1 is again selected, in parallel to the erasure of the digital videosignal at the first bit in the pixels. Thus, the pixels in the first rowagain perform the display operation. The non-display period Td1 is thuscompleted, and a display period Tr2 starts.

[0189] Thereafter, all of the writing gate signal lines are sequentiallyselected in the similar manner as described before, and the digitalvideo signal at the second bit is input into all of the pixels. A timeperiod required for inputting the digital video signal at the second bitinto the pixels in all of the rows is referred to as a writing periodTa2.

[0190] On the other hand, before the digital video signal at the secondbit is input into the pixels in all of the rows, in other words, beforethe writing period Ta2 is completed, the erasure gate signal line Ge2 isselected in parallel to the input of the digital video signal at thesecond bit into the pixels. Thus, all of the light emitting elementsincluded in the pixels in the first row are placed in the non-emissionstate. Thus, the pixels in the first row do not perform a displayoperation. The display period Tr2 for the pixels in the first row isthen completed, and the non-display period Td2 starts.

[0191] Thereafter, all of the erasure gate signal lines are sequentiallyselected. A time period required for selecting all of the erasure gatesignal lines (Ga1 to Gax) and erasing the digital video signal at thesecond bit held at the pixels in all of the rows is an erasure periodTe2.

[0192] The above-described operations are repeated until the digitalvideo signal at the m-th bit is input into the pixels, so that thedisplay period Tr and the non-display period Td appear alternately. Thedisplay period Tr1 is a period from the start of the writing period Ta1until the erasure period Te1 starts. The non-display period Td1 is aperiod from the start of the erasure period Te1 until the display periodTr2 starts. Similarly as the display period Tr1 and the non-displayperiod Td1, lengths of the display periods Tr2, Tr3, . . . , Tr(m−1) andthe non-display periods Td2, Td3, . . . , Td(m−1) are defined by meansof the writing periods Ta1, Ta2, . . . , Tam and the erasure periodsTe1, Te2, . . . , Te(m−1).

[0193] After the digital video signal at the m-th bit has been inputinto the pixels in the first row, the erasure gate signal line Ge1 isnot selected. For the purpose of simplification of the description, thecase with m=n−2 is described as an example in the present embodiment.However, the present invention is not limited to such a case. In thepresent invention, as the value of m, any number in the range from 2 ton can be arbitrarily selected.

[0194] When the digital video signal at the (n−2)-th bit is input intothe pixels in the first row, the pixels in the first row are placed inthe display period Tr(n−2) to perform a display operation. Until thenext digital video signal at the next bit is input, the digital videosignal at the (n−2)-th bit is held at the pixels.

[0195] When the digital video signal at the (n-l)-th bit is input intothe pixels in the first row, the digital video signal at the (n−2)-thbit held at the pixels are rewritten into the digital video signal atthe (n−1)-th. The pixels in the first bit are then placed in the displayperiod Tr(n−1) to perform a display operation. Until the next digitalvideo signal at the next bit is input, the digital video signal at the(n−2)-th bit is held at the pixels.

[0196] The above-described operations are repeated until the digitalvideo signal at the n-th bit is input into the pixels. The displayperiod Tr(n−2) is a period from the start of the writing period Ta(n−2)until the writing period Ta(n−1) starts. Similarly as the display periodTr(n−2), lengths of the display periods Tr(n−1) and Trn are defined bymeans of the writing period Ta.

[0197] In the present embodiment, it is necessary that the sum of all ofthe writing periods is shorter than one frame period and ratios amongthe respective display periods are set to satisfy the relationship ofTr1:Tr2:Tr3: . . . :Tr(n−1):Trn=2⁰:2¹:2²: . . . :2^((n−2)):2^((n−1)).Through the combination of the display periods, a desired gradationdisplay among the total of 2^(n) gradations can be realized.

[0198] After all of the display periods (Tr1 through Trn) are completed,one image can be displayed. In the driving method in accordance with thepresent invention, a time period required for displaying one image isreferred to as one frame period (F).

[0199] After a certain one frame period (F) is completed, the digitalvideo signal at the first bit is again input into the pixels, so thatthe pixels in the first row are again placed in the display period Tr1.The above-mentioned operations are again repeated.

[0200] In a normal light emitting device, it is preferable to provide 60or more frame periods per one second. If the number of images to bedisplayed in one second is smaller than 60, flickering of the image maybecome visually significant.

[0201] The gradation to be displayed by a particular pixel in a certainone frame period is determined by obtaining the sum of the displayperiods during which the light emitting element emits light in thatframe period. For example, assuming that n=8 and the brightness obtainedwhen the pixel emits light in all of the display periods is expressed as100%, the brightness of 1% can be realized in the case where the pixelemits light in Tr1 and Tr2, while the brightness of 60% can be realizedwhen Tr3, Tr5, and Tr8 are selected.

[0202] The writing period Tam during which the digital video signal atthe m-th bit is input into the pixels is required to be shorter than thedisplay period Trm. Accordingly, the number of bits m is required to besuch a number from 1 to n that can allow the writing period Tam to beshorter than the display period Trm.

[0203] The display periods (Tr1 through Trn) may appear on any order.For example, during one frame period, the display periods may becontrolled to appear in such an order that Tr1 is followed by Tr4, Tr3,Tr2, . . . . It should be noted, however, that the appearing order ofthe display periods is preferably set so as not to cause the erasureperiods (Te1 through Ten) to be overlapped with each other.

[0204] In the present embodiment, the display period Tr and the writingperiod Ta are partially overlapped with each other. In other words, thepixels can perform a display operation even during the writing period.Accordingly, a ratio of the sum of the display periods within one frameperiod (duty ratio) is not determined only by the length of the writingperiod.

Embodiment 3

[0205] In the present embodiment, the structure of the source signalline driver circuit contained in the light emitting device as describedin Embodiment 1 will be described in detail. FIG. 13 shows a circuitdiagram of the source signal line driver circuit in the presentembodiment. In FIG. 13, the same components as those shown in FIG. 1 aredesignated with the same reference numerals.

[0206] Reference numeral 102-1 denotes a shift register, to which aclock signal (CLK), a signal (CLKB) obtained by inverting the polarityof the clock signal, a start pulse signal (SP), a bi-direction shiftsignal (SL/R) are input through the illustrated wirings, respectively.

[0207] Reference numerals 102-2 and 102-3 denote a latch (A) and a latch(B), respectively. In the present embodiment, a combination of thelatches (A) 102-2 and a combination of the latches (B) 102-3 correspondsto four source signal lines. However, the number of source signal linesto which a combination of the latches (A) 102-2 and a combination of thelatches (B) 102-3 corresponds is not limited to the above number in thepresent embodiment. In addition, although a level shift for changing awidth of a voltage amplitude of a signal is not provided in the presentembodiment, such a level shift may be appropriately provided by adesigner.

[0208] The digital video signal (DV) to be supplied externally to thesource signal line driver circuit is input into the latch (A) 102-2through the illustrated wirings. A latch signal S_LAT and a signalS_LATb obtained by inverting the polarity of the S_LAT are respectivelyinput into the latch (B) 102-3 through the illustrated wirings.

[0209] The structure of the latch (A) 102-2 will be described in detailwith reference to a portion 801 of the latch (A) 102-2. The portion 801of the latch (A) 102-2 includes two clocked inverters and two inverters.

[0210] A plan view of the portion 801 of the latch (A) 102-2 is shown inFIG. 14. Reference numerals 831 a and 831 b respectively denote activelayers of TFTs that constitute one of the inverters included in theportion 801 of the latch (A) 102-2. Reference numeral 836 denotes acommon gate electrode of the TFTs that constitute the particular one ofthe inverters.

[0211] Reference numerals 832 a and 832 b respectively denote activelayers of TFTs that constitute the other one of the inverters includedin the portion 801 of the latch (A) 102-2. Reference numerals 837 a and837 b denote gate electrodes formed over the active layers 832 a and 832b, respectively. The gate electrodes 837 a and 837 b are electricallyconnected to each other.

[0212] Reference numerals 833 a and 833 b respectively denote activelayers of TFTs that constitute one of the clocked inverters included inthe portion 801 of the latch (A) 102-2. Gate electrodes 838 a and 838 bare provided over the active layer 833 a to form a double gatestructure. Similarly, gate electrodes 838 b and 839 are provided overthe active layer 833 b to form a double gate structure.

[0213] Reference numerals 834 a and 834 b respectively denote activelayers of TFTs that constitute the other one of the clocked invertersincluded in the portion 801 of the latch (A) 102-2. Gate electrodes 839and 840 are provided over the active layer 834 a to form a double gatestructure. Similarly, gate electrodes 840 and 841 are provided over theactive layer 834 b to form a double gate structure.

[0214] Reference numeral 102-4 denotes the switching circuit. FIGS. 15Aand 15B shows circuit diagrams of the switching circuit in accordancewith the present embodiment.

[0215] The switching circuit 102-4 of the present embodiment as shown inFIG. 15A includes an inverter 851, a first analog switch 852, and asecond analog switch 853. A shift signal SS and a signal SSB obtained byinverting the polarity of the shift signal SS are input through theillustrated wirings.

[0216] Equivalent circuit diagrams of the first analog switch 852 andthe second analog switch 853 are shown in FIG. 16. Each of the firstanalog switch 852 and the second analog switch 853 includes an n-channeltype TFT and a p-channel type TFT. A signal to be input from an inputterminal (IN) is sampled by means of a signal to be input from a firstcontrol input terminal (Vin) or a second control input terminal (Vinb),and the resultant signals is output from an output terminal (OUT).

[0217] The digital video signal from the latch (B) 102-3 is input viathe inverter 851 into the first analog switch 852 through the inputterminal (IN). Simultaneously, the digital video signal from the latch(B) 102-3 is input into the second analog switch 853 through the inputterminal (IN).

[0218] The shift signal SS and the signal SSB obtained by inverting thepolarity of the shift signal SS are input into the first analog switch852 and the second analog switch 853, respectively, through the firstcontrol input terminal (Vin) or the second control input terminal(Vinb). The digital video signal is sampled by this shift signal SS, andthe sampled digital video signal is output from output terminals (OUT)of the first analog switch 852 and the second analog switch 853.

[0219] The digital video signal input into the switching circuit 102-4is output therefrom after the polarity thereof is inverted, oralternatively, without having the polarity inverted. The shift signal SSdetermines whether the polarity of the digital video signal is to beinverted or not in the switching circuit 102-4.

[0220] The switching circuit 102-4 as shown in FIG. 15B includes aninverter 861, a first NAND 862, a second NAND 863, and the third NOR864. A shift signal SS and a signal SSB obtained by inverting thepolarity of the shift signal SS are input through the illustratedwirings.

[0221] The digital video signal from the latch (B) 102-3 is providedthrough the inverter 861. Simultaneously, the signal SSB obtained byinverting the polarity of the shift signal SS is input into the firstNAND 862.

[0222] Simultaneously with the input of the digital video signal intothe first NAND 862 through the inverter 861, the digital video signal isalso input into the second NAND 863. Simultaneously, the shift signal SSis also input into the second NAND 863.

[0223] Signals output from the first NAND 862 and the second NAND 863are simultaneously input into the third NOR 864. A signal output fromthe third NOR 864 is input into the source signal line.

[0224] The digital video signal input into the switching circuit 102-4is output therefrom after the polarity thereof is inverted, oralternatively, without having the polarity inverted. The shift signal SSdetermines whether the polarity of the digital video signal is to beinverted or not in the switching circuit 102-4.

[0225] The structure of the switching circuit is not limited to thoseshown in FIGS. 15A and 15B. The switching circuit may have anyappropriate structure as long as it can allow the digital video signalinput thereto to be output therefrom with either the inverted polarityor the non-inverted polarity.

[0226] The present embodiment can be freely combined with Embodiments 1or 2.

Embodiment 4

[0227] In the present embodiment, the structure of the source signalline driver circuit contained in the light emitting device as describedin Embodiment 2 will be described in detail. FIG. 17 shows a circuitdiagram of the source signal line driver circuit in the presentembodiment. In FIG. 17, the same components as those shown in FIG. 1 aredesignated with the same reference numerals.

[0228] Reference numeral 102-1 denotes a shift register, to which aclock signal (CLK), a signal (CLKB) obtained by inverting the polarityof the clock signal, a start pulse signal (SP), a bi-direction shiftsignal (SL/R) are input through the illustrated wirings, respectively.

[0229] Reference numerals 102-2 and 102-3 denote a latch (A) and a latch(B), respectively. In the present embodiment, a combination of thelatches (A) 102-2 and a combination of the latches (B) 102-3 correspondto four source signal lines. However, the number of source signal linesto which a combination of the latches (A) 102-2 and a combination of thelatches (B) 102-3 correspond is not limited to the above number in thepresent embodiment. In addition, although a level shift for changing awidth of a voltage amplitude of a signal is not provided in the presentembodiment, such a level shift may be appropriately provided by adesigner.

[0230] The digital video signal (DV) to be supplied externally to thesource signal line driver circuit is input into the latch (A) 102-2through the illustrated wirings. A latch signal S_LAT and a signalS_LATb obtained by inverting the polarity of the S_LAT are respectivelyinput into the latch (B) 102-3 through the illustrated wirings.

[0231] The detailed structure of the latch (A) 102-2 is the same as thatshown in FIG. 14. Accordingly, the description thereof is omitted here.

[0232] Reference numeral 106 denotes the clock signal control circuit,that can supply a constant electrical potential (fixed electricalpotential), instead of the clock signal (CLK), to the shift register102-1 for a constant time period.

[0233] More specifically, the constant electrical potential (fixedelectrical potential) instead of the clock signal is input into theshift register 102-1 for a constant time period by means of the clocksignal control circuit 106, so that the timing signal that is to be usedfor inputting the digital video signal at less significant bits in therange from the first bit to the m-th bit into the latch (A) 102-2 isprevented from being input into the latch (A) 102-2. Accordingly, amongthe digital video signal n input from external source signal line drivercircuit, only the digital video signal at more significant bits in therange from the (m+1)-th bit to the n-th bit can be written into thelatch (A) 102-2.

[0234]FIGS. 18A and 18B show detailed circuit diagrams of the clocksignal control circuit 106 in accordance with the present embodiment.

[0235] The clock signal control circuit 106 of the present embodiment asshown in FIG. 18A includes a NAND 1801 and an inverter 1802. A selectionsignal is input through the illustrated wiring.

[0236] The clock signal to be input externally to the source signal linedriver circuit is input into the NAND 1801 through an input terminal(IN). Simultaneously, the selection signal is also input into the NAND1801. A signal output from the NAND 1801 is provided at an outputterminal (OUT) after the polarity thereof is inverted by the inverter1802 to be input into the shift register 102-1.

[0237] The selection signal determines whether the clock signal is to beinput into the shift register 102-1, or the constant electricalpotential (fixed electrical potential) is to be instead suppliedthereto.

[0238] The clock signal control circuit 106 of the present embodiment asshown in FIG. 18B includes a first analog switch 1811, a second analogswitch 1812, and an inverter 1813. A selection signal is input throughthe illustrated wiring.

[0239] Equivalent circuit diagrams of the first analog switch 1811 andthe second analog switch 1812 are the same as that shown in FIG. 16.Each of the first analog switch 1811 and the second analog switch 1812includes an n-channel type TFT and a p-channel type TFT. A signal to beinput from an input terminal (IN) is sampled by means of a signal to beinput from a first control input terminal (Vin) or a second controlinput terminal (Vinb), to be then output from an output terminal (OUT).

[0240] The selection signal is input into the first analog switch 1811and the second analog switch 1812 through the first control inputterminal (Vin). Simultaneously, the selection signal is also input intothe first analog switch 1811 and the second analog switch 1812 throughthe second control input terminal (Vinb) after the polarity thereof isinverted. Further simultaneously, the clock signal to be suppliedexternally to the source signal line driver circuit is input into thefirst analog switch 1811 through the input terminal (IN). The secondanalog switch 1812 is supplied with the constant electrical potential(fixed electrical potential) through the input terminal (IN).

[0241] Signals respectively output from output terminals (OUT) of thefirst analog switch 1811 and the second analog switch 1812 are bothoutput from an output terminal of the clock signal control circuit 106.

[0242] The selection signal determines whether the clock signal is to beinput into the shift register 102-1, or the constant electricalpotential (fixed electrical potential) is to be instead suppliedthereto.

[0243] The structure of the clock signal control circuit is not limitedto those shown in FIGS. 18A and 18B.

[0244] The present embodiment can be freely combined with Embodiments 1through 3.

Embodiment 5

[0245] In the present embodiment, the structure of the source signalline driver circuit contained in the light emitting device as describedin Embodiment 3 will be described in detail. FIG. 19 shows a circuitdiagram of the source signal line driver circuit in the presentembodiment. In FIG. 19, the same components as those shown in FIG. 1 aredesignated with the same reference numerals.

[0246] Reference numeral 102-1 denotes a shift register, to which aclock signal (CLK), a signal (CLKB) obtained by inverting the polarityof the clock signal, a start pulse signal (SP), a bi-direction shiftsignal (SL/R) are input through the illustrated wirings, respectively.

[0247] Reference numerals 102-2 and 102-3 denote a latch (A) and a latch(B), respectively. In the present embodiment, a combination of thelatches (A) 102-2 and a combination of the latches (B) 102-3 correspondto four source signal lines. However, the number of source signal linesto which a combination of the latches (A) 102-2 and a combination of thelatches (B) 102-3 correspond is not limited to the above number in thepresent embodiment. In addition, although a level shift for changing awidth of a voltage amplitude of a signal is not provided in the presentembodiment, such a level shift may be appropriately provided by adesigner.

[0248] The digital video signal (DV) to be supplied externally to thesource signal line driver circuit is input into the latch (A) 102-2through the illustrated wirings. A latch signal S_LAT and a signalS_LATb obtained by inverting the polarity of the S_LAT are respectivelyinput into the latch (B) 102-3 through the illustrated wirings.

[0249] The detailed structure of the latch (A) 102-2 is the same as thatshown in FIG. 14. Accordingly, the description thereof is omitted here.

[0250] Reference numeral 107 denotes the timing signal control circuit,that can supply a constant electrical potential (fixed electricalpotential), instead of the timing signal, to the latch (A) 102-2 for aconstant time period.

[0251] More specifically, the constant electrical potential (fixedelectrical potential) instead of the timing signal is input into theshift register 102-2 for a constant time period by means of the timingsignal control circuit 107, so that the timing signal that is to be usedfor inputting the digital video signal at less significant bits in therange from the first bit to the m-th bit into the latch (A) 102-2 isprevented from being input into the latch (A) 102-2. Accordingly, onlythe digital video signal at more significant bits in the range from the(m+1)-th bit to the n-th bit can be written into the latch (A) 102-2.

[0252] A structure of the timing signal control circuit 107 in thepresent embodiment is the same as those shown in FIGS. 18A and 18B.Accordingly, the detailed description about the structure of the timingsignal control circuit 107 should be found in Embodiment 4. It should benoted, however, that in the present embodiment, the timing signal fromthe shift register 102-1 is input into the input terminal (IN) in thecircuits as shown in FIGS. 18A and 18B. A signal output from an outputterminal (OUT) in the circuits as shown in FIGS. 18A and 18B is inputinto the latch (A) 102-2. The selection signal determines whether thetiming signal is to be input into the latch (A) 102-2, or the constantelectrical potential (fixed electrical potential) is to be insteadsupplied thereto.

[0253] The structure of the timing signal control circuit is not limitedto those shown in FIGS. 18A and 18B.

[0254] The present embodiment can be freely combined with Embodiments 1through 3.

Embodiment 6

[0255] In the present embodiment, the structure of the source signalline driver circuit contained in the light emitting device as describedin Embodiment 4 will be described in detail. FIG. 20 shows a circuitdiagram of the source signal line driver circuit in the presentembodiment. In FIG. 20, the same components as those shown in FIG. 1 aredesignated with the same reference numerals.

[0256] Reference numeral 102-1 denotes a shift register, to which aclock signal (CLK), a signal (CLKB) obtained by inverting the polarityof the clock signal, a start pulse signal (SP), a bi-direction shiftsignal (SL/R) are input through the illustrated wirings, respectively.

[0257] Reference numerals 102-2 and 102-3 denote a latch (A) and a latch(B), respectively. In the present embodiment, a combination of thelatches (A) 102-2 and a combination of the latches (B) 102-3 correspondto four source signal lines. However, the number of source signal linesto which a combination of the latches (A) 102-2 and a combination of thelatches (B) 102-3 correspond is not limited to the above number in thepresent embodiment. In addition, although a level shift for changing awidth of a voltage amplitude of a signal is not provided in the presentembodiment, such a level shift may be appropriately provided by adesigner.

[0258] The digital video signal (DV) to be supplied externally to thesource signal line driver circuit is input into the latch (A) 102-2through the illustrated wirings. A latch signal S_LAT and a signalS_LATb obtained by inverting the polarity of the S_LAT are respectivelyinput into the latch (B) 102-3 through the illustrated wirings.

[0259] The detailed structure of the latch (A) 102-2 is the same as thatshown in FIG. 14. Accordingly, the description thereof is omitted here.

[0260] Reference numeral 108 denotes the start pulse signal controlcircuit, that can supply a constant electrical potential (fixedelectrical potential), instead of the start pulse signal (SP), to theshift register 102-1 for a constant time period.

[0261] More specifically, the constant electrical potential (fixedelectrical potential) instead of the start pulse signal is input intothe shift register 102-2 for a constant time period by means of thestart pulse signal control circuit 108, so that the timing signal thatis to be used for inputting the digital video signal at less significantbits in the range from the first bit to the m-th bit into the latch (A)102-2 is prevented from being input into the shift register 102-1.Accordingly, only the digital video signal at more significant bits inthe range from the (m+1)-th bit to the n-th bit can be written into thelatch (A) 102-2.

[0262] A structure of the start pulse signal control circuit 108 in thepresent embodiment is the same as those shown in FIGS. 18A and 18B.Accordingly, the detailed description about the structure of the startpulse signal control circuit 108 should be found in Embodiment 4. Itshould be noted, however, that in the present embodiment, the startpulse signal is input into the input terminal (IN) in the circuits asshown in FIGS. 18A and 18B. A signal output from an output terminal(OUT) in the circuits as shown in FIGS. 18A and 18B is input into theshift register 102-1. The selection signal determines whether the startpulse signal is to be input into the shift register 102-1, or theconstant electrical potential (fixed electrical potential) is to beinstead supplied thereto.

[0263] The structure of the start pulse signal control circuit is notlimited to those shown in FIGS. 18A and 18B.

[0264] The present embodiment can be freely combined with Embodiments 1through 3.

Embodiment 7

[0265] In the present embodiment, another example for the thirdstructure in accordance with the present invention, which is differentfrom that as described in Embodiment 5, will be described with referenceto FIG. 21. In FIG. 21, the same component as shown in FIG. 5 aredesignated with the same reference numerals.

[0266] In FIG. 21, reference numeral 502 denotes a buffer amplifier,reference numeral 503 denotes a monitoring light emitting device,reference numeral 504 denotes a constant current source, and referencenumeral 505 denotes an adding circuit. One of electrodes of themonitoring light emitting element 503 is connected to the constantcurrent source 504, so that a constant current always flows through themonitoring light emitting element 503. When a temperature of an organiccompound layer contained in the light emitting element changes, themagnitude of the current to flow through the monitoring light emittingelement 503 does not change, but rather, an electrical potential of theelectrode of the monitoring light emitting element 503 connected to theconstant current source 504 changes.

[0267] On the other hand, the buffer amplifier 502 includes two inputterminals and one output terminal. One of the two input terminals is anon-inverted input terminal (+), while the other is an inverted inputterminal (−). An electrical potential at one of electrodes of themonitoring light emitting device 503 is supplied to the non-invertedinput terminal of the buffer amplifier 502.

[0268] An output terminal of the buffer amplifier 502 is connected tothe inverted input terminal (−).

[0269] The buffer amplifier 502 is a circuit for preventing anelectrical potential at a pixel electrode of the monitoring lightemitting element 503 connected to the constant current source 504 fromchanging in accordance with a load such as a wiring capacitance or thelike. Accordingly, the electrical potential provided to the non-invertedinput terminal of the buffer amplifier 502 is output from an outputterminal to be supplied to the power source line as the power sourcepotential, without being changed in accordance with a load of a wiringcapacitance and adding circuit 505 or the like, to the adding circuit505.

[0270] The electrical potential supplied to the adding circuit 505 fromthe output terminal of the buffer amplifier 502 is further supplied tothe pixel electrode in the pixel portion of the light emitting element,after a certain constant potential difference is added thereto orsubtracted therefrom.

[0271]FIG. 22 shows the detailed circuit diagram of the adding circuitin the present embodiment. The adding circuit 505 includes a firstresistor 521, a second resistor 522, a power source 525 for the addingcircuit, and a non-inverting amplifier circuit 520. The non-invertingamplifier circuit 520 includes a third resistor 523, a fourth resistor524, a power source 526 for the non-inverting amplifier circuit, and anamplifier 527.

[0272] One of the terminals of the first resistor 521 functions as aninput terminal (IN) of the adding circuit. The other terminal of thefirst resistor 521 is connected to one of the terminals of the secondresistor 522. The other terminal of the second resistor 522 is connectedto the power source 525 for the adding circuit. An output obtainablebetween the first resistor 521 and the second resistor 522 is input intothe non-inverted input terminal (+) of the amplifier 527 of thenon-inverting amplifier circuit 520.

[0273] One of the terminals of the third resistor 523 is connected to anoutput terminal of the amplifier 527, while the other terminal of thethird resistor 523 is connected to the inverted input terminal of theamplifier 527. An output obtainable between the third resistor 523 andthe inverted input terminal of the amplifier 527 is input to one of theterminals of the fourth resistor 524. The other terminal of the fourthresistor 524 is connected to the power source 526 for the non-invertingamplifier circuit. An output obtainable between the third resistor 523and the output terminal of the amplifier 527 is output from an outputterminal (OUT) of the adding circuit 505.

[0274] In accordance with the above-described structure, even when atemperature of the monitoring light emitting element 503 or the organiccompound layer of the light emitting element in the pixel portionchanges due to a change in an environmental temperature, the powersource potential is changed so as to allow a constant current to flowthrough the light emitting element. Thus, even when the environmentaltemperature of the light emitting device increases, power consumption ofthe light emitting device can be prevented from increasing, andfurthermore, the brightness of the light emitting element can bemaintained at a constant level. Moreover, by further providing theadding circuit 505, the electrical potential of pixel electrodes oflight emitting element is not required to be at the same level as theelectrical potential of the electrode connected to the constant currentsource 504 of the monitoring light emitting element 503. Thus, themagnitude of the current to flow through the buffer amplifier 502, themonitoring light emitting element 503, and the constant current source504 can be suppressed, thereby resulting in the power consumption beingsuppressed.

[0275] The structure of the adding circuit 505 is not limited to thatshown in FIG. 22.

[0276] The present embodiment can be freely combined with Embodiments 1through 6.

Embodiment 8

[0277] In Embodiment 8, a method of manufacturing a pixel portion andTFTs (n-channel TFTs and p-channel TFTs) of a driver circuit formed inthe periphery of the pixel portion, on the same substrate simultaneouslyis explained in detail.

[0278] First, as shown in FIG. 23A, a base film 401 made from aninsulating film such as a silicon oxide film, a silicon nitride film, ora silicon oxynitride film is formed on a substrate 400 made from glasssuch as barium borosilicate glass or aluminum borosilicate glass,typically Corning Corp. #7059 glass or #1737 glass, or made from aquartz substrate. For example, a silicon oxynitride film made from SiH₄,NH₃, and N₂O by plasma CVD is formed with a thickness of 10 to 200 nm(preferably from 50 to 100 nm), and a hydrogenated silicon oxynitridefilm with a thickness of 50 to 200 nm (preferably between 100 and 150nm), made from SiH₄ and N₂O, is similarly formed and laminated. Notethat the base film is shown as one layer in FIG. 23A. The base film 401is shown as a two layer structure in Embodiment 8, but it may also beformed as a single layer of the above insulating films, and it may alsobe formed having a lamination structure in which two layers or more arelaminated.

[0279] Semiconductor layers 402 to 405 are formed from a crystallinesemiconductor film which is formed by a semiconductor film having anamorphous structure with a laser crystallization method or a knownthermal crystallization method. The thickness of the semiconductorlayers 402 to 405 is formed to a thickness of 25 to 80 nm (preferablybetween 30 and 60 nm). There are no limitations in the crystallinesemiconductor film material, but it is preferable to form the film fromsilicon or silicon germanium (SiGe) alloy.

[0280] As for known crystallization methods, there is a thermalcrystallization method using an electric furnace, a laser annealingcrystallization method using laser light, a lamp annealingcrystallization method using infrared light, and a crystallizationmethod using a catalyst metal.

[0281] A laser such as a pulse emission type or continuous emission typeexcimer laser, a YAG laser, and a YVO₄ laser can be used in the lasercrystallization method to manufacture a crystalline semiconductor film.A method of condensing laser light emitted from a laser emission deviceinto a linear shape by an optical system and then irradiating the lightto the semiconductor film may be used when these types of lasers areused. The crystallization conditions may be suitably selected by theoperator, but when using the excimer laser, the pulse emission frequencyis set to 300 Hz, and the laser energy density is set from 100 to 400mJ/cm² (typically between 200 and 300 mJ/cm²). Further, the secondharmonic is utilized when using the YAG laser, the pulse emissionfrequency is set from 30 to 300 kHz, and the laser energy density may beset from 300 to 600 mJ/cm² (typically between 350 and 500 mJ/cm²). Thelaser light collected into a linear shape with a width of 100 to 1000μm, for example 400 μm, is then irradiated over the entire surface ofthe substrate. This is performed with an overlap ratio of 50 to 98% forthe linear shape laser light.

[0282] Then, a gate insulating film 406 is formed covering thesemiconductor layers 402 to 405. A gate insulating film 406 is formed byan insulating film containing silicon with a thickness of 40 to 150 nmby plasma CVD or sputtering. A 120 nm thick silicon oxynitride film isformed in Embodiment 8. The gate insulating film 406 is not limited tothis type of silicon oxynitride film, of course, and other insulatingfilms containing silicon may also be used, in a single layer or in alamination structure. For example, when using a silicon oxide film, itcan be formed by plasma CVD with a mixture of TEOS (tetraethylorthosilicate) and O₂, at a reaction pressure of 40 Pa, with thesubstrate temperature set from 300 to 400° C., and by discharging at ahigh frequency (13.56 MHZ) electric power density of 0.5 to 0.8 W/cm².Good characteristics as a gate insulating film can be obtained bysubsequently performing thermal annealing, at between 400 and 500° C.,of the silicon oxide film thus manufactured.

[0283] A first conducting film 407 and a second conducting film 408 arethen formed on the gate insulating film 406 in order to form gateelectrodes. The first conducting film 407 is formed from Ta (tantalum)with a thickness of 50 to 100 nm, and the second conducting film 408 isformed from W (tungsten) having a thickness of 100 to 300 nm, inEmbodiment 8.

[0284] The Ta film is formed by sputtering, and sputtering of a Tatarget is performed in Ar. If appropriate amounts of Xe and Kr are addedto Ar at the time of sputtering, the internal stress of the Ta film isrelaxed, and film peeling can be prevented. The resistivity of an αphase Ta film is on the order of 20 μΩcm, and it can be used in the gateelectrode, but the resistivity of a β phase Ta film is on the order of180 μΩcm and it is unsuitable for the gate electrode. An α phase Ta filmcan easily be obtained if a tantalum nitride film, which possesses acrystal structure near that of a phase Ta, is formed with a thickness of10 to 50 nm as a base for Ta in order to form α phase Ta.

[0285] The W film is formed by sputtering with a W target, which canalso be formed by thermal CVD using tungsten hexafluoride (WF₆).Whichever is used, it is necessary to be able to make the film becomelow resistance in order to use it as the gate electrode, and it ispreferable that the resistivity of the W film be made equal to or lessthan 20 μΩcm. The resistivity can be lowered by enlarging the crystalgrains of the W film, but for cases in which there are many impurityelements such as oxygen in the W film, crystallization is inhibited, andthe film becomes high resistance. A W target having a purity of 99.9999%or 99.99% is thus used in sputtering. In addition, by forming the W filmwhile taking sufficient care that no impurities from the gas phase areintroduced at the time of film formation, the resistivity of 9 to 20μΩcm can be achieved.

[0286] Note that, although the first conducting film 407 is Ta and thesecond conducting film 408 is W in Embodiment 8, the conducting filmsare not limited to these, and both may also be formed from an elementselected from the group consisting of Ta, W, Ti, Mo, Al, and Cu, or froman alloy material having one of these elements as its main constituent,or from a chemical compound of these elements. Further, a semiconductorfilm, typically a poly-crystalline silicon film into which an impurityelement such as phosphorus is doped, may also be used. An example ofpreferable combinations other than that used in Embodiment 8 include:forming the first conducting film by tantalum nitride (TaN) andcombining it with the second conducting film formed from W; forming thefirst conducting film by tantalum nitride (TaN) and combining it withthe second conducting film formed from Al; and forming the firstconducting film by tantalum nitride (TaN) and combining it with thesecond conducting film formed from Cu. (See FIG. 23B.)

[0287] Masks 409 to 412 are formed next from resist, and a first etchingprocess is performed in order to form electrodes and wirings. An ICP(inductively coupled plasma) etching method is used in Embodiment 8. Agas mixture of CF₄ and Cl₂ is used as an etching gas, and a plasma isgenerated by applying a 500 W RF electric power (13.56 MHZ) to a coilshape electrode at a pressure of 1 Pa. A 100 W RF electric power (13.56MHZ) is also applied to the substrate side (test piece stage),effectively applying a negative self-bias voltage. The W film and the Tafilm are both etched on the same order when CF₄ and Cl₂ are combined.

[0288] Not shown in FIG. 23C, edge portions of the first conductinglayer and the second conducting layer are made into a tapered shape inaccordance with the effect of the bias voltage applied to the substrateside under the above etching conditions by using a suitable resist maskshape. The angle of the tapered portions is from 15 to 45°. The etchingtime may be increased by approximately 10 to 20% in order to performetching without any residue remaining on the gate insulating film. Theselectivity of a silicon oxynitride film with respect to a W film isfrom 2 to 4 (typically 3), and therefore approximately 20 to 50 nm ofthe exposed surface of the silicon oxynitride film is etched by thisover-etching process. Further, not shown in FIG. 23C, regions of thegate insulating film 406 not covered by first shape conducting layers414 to 417 are made thinner by 20 to 50 nm after etching.

[0289] The first shape conducting layers 414 to 417 (first conductinglayers 414 a to 417 a and second conducting layers 414 b to 417 b) arethus formed from the first conducting layer and the second conductinglayer in accordance with the first etching process.

[0290] A second etching process is performed next, as shown in FIG. 23D.The ICP etching method is similarly used, a mixture of CF₄, Cl₂, and O₂is used as the etching gas, and a plasma is generated by supplying a 500W RF electric power (13.56 MHZ) to a coil shape electrode at a pressureof 1 Pa. A 50 W RF (13.56 MHZ) electric power is applied to thesubstrate side (test stage), and a self-bias voltage which is lower incomparison to that of the first etching process is applied. The W filmis etched anisotropically under these etching conditions, and Ta (thefirst conducting layers) is anisotropically etched at a slower etchingspeed, forming second shape conducting layers 419 to 422 (firstconducting layers 419 a to 422 a and second conducting layers 419 b to422 b). Further, although not shown in FIG. 23D, the gate insulatingfilm 406 is additionally etched on the order of 20 to 50 nm, becomingthinner, in regions not covered by the second shape conducting layers419 to 422.

[0291] The etching reaction of the W film and the Ta film in accordancewith the mixed gas of CF₄ and Cl₂ can be estimated from the radicalsgenerated, and from the ion types and vapor pressures of the reactionproducts. Comparing the vapor pressures of W and Ta fluorides andchlorides, the W fluoride compound WF₆ is extremely high, and the vaporpressures of WCl₅, TaF₅, and TaCl₅ are of similar order. Therefore the Wfilm and the Ta film are both etched by the CF₄ and Cl₂ gas mixture.However, if a suitable quantity of O₂ is added to this gas mixture, CF₄and O₂ react, forming CO and F, and a large amount of F radicals or Fions are generated. As a result, the etching speed of the W film havinga high fluoride vapor pressure becomes fast. On the other hand, even ifF increases, the etching speed of Ta does not relatively increase.Further, Ta is easily oxidized compared to W, and therefore the surfaceof Ta is oxidized by the addition of O₂. The etching speed of the Tafilm is further reduced because Ta oxides do not react with fluorine andchlorine. It therefore becomes possible to have a difference in etchingspeeds between the W film and the Ta film, and it becomes possible tomake the etching speed of the W film larger than that of the Ta film.

[0292] Then, the masks 409 a to 412 a are removed, and a first dopingprocess is performed as shown in FIG. 24A, adding an impurity elementwhich imparts n-type conductivity. For example, doping may be performedat an acceleration voltage of 70 to 120 keV and with a dose amount of1×10¹³ atoms/cm². The doping process is performed using the second shapeconducting layers 419 to 422 as masks against the impurity element, andso as to also add the impurity element in regions below the secondconducting layers 419 a to 422 a. First impurity regions 425 to 428,which overlap with the second conducting layers 419 a to 422 a, andsecond impurity regions 429 to 432, which have a higher impurityconcentration than the first impurity regions, are thus formed. Notethat the impurity element which imparts n-type conductivity is addedafter removing the masks 409 a to 412 a in Embodiment 8, but the presentinvention is not limited to this. The impurity element which impartsn-type conductivity may also be added in the step of FIG. 24A, and thenthe masks 409 a to 412 a may be removed.

[0293] A mask 433 is next formed on the semiconductor layer 404 so as tocover the second conducting layers 421 a and 421 b. The mask 433partially overlaps with the second impurity region 431, sandwiching thegate insulating film 406. A second doping process is then performed, andan impurity element which imparts n-type conductivity is added. Dopingof the impurity element which imparts n-type conductivity is performedat conditions in which the dose amount is raised higher than that of thefirst doping process, and at a low acceleration voltage. (See FIG. 24B.)The doping can be carried out by ion doping or ion implantation. Iondoping is performed under conditions of a dose amount from 1×10¹³ to5×10¹⁴ atoms/cm² and an acceleration voltage of 60 to 100 keV. Aperiodic table group 15 element, typically phosphorus (P) or arsenic(As) is used as the impurity element which imparts n-type conductivity,and phosphorus (P) is used here. The second shape conducting layers 419to 422 become masks with respect to the impurity element which impartsn-type conductivity in this case, and source regions 434 to 437, drainregions 438 to 441, and Lov regions 442 to 445 are formed in aself-aligning manner. Further, Loff region 446 is formed in accordancewith the mask 433. The impurity element which imparts n-typeconductivity is added to the source regions 434 to 437, and to the drainregions 438 to 441 with a concentration in the range of 1×10²⁰ to 1×10²¹atoms/cm³.

[0294] It is possible to freely set the length of the Loff region 446 bycontrolling the size of the mask 433 according to Embodiment 8.

[0295] Note that in the specification, the LDD region overlapping with agate electrode through a gate insulating film is referred to as an Lovregion, and the LDD region not overlapping with a gate electrode througha gate insulating film is referred to as an Loff region.

[0296] The impurity element which imparts n-type conductivity is addedat a concentration of 1×10¹⁷ to 1×10¹⁹ atoms/cm³ in the Loff region, andat a concentration of 1×10¹⁶ to 1×10¹⁸ atoms/cm³ in the Lov region.

[0297] Note that, in FIG. 24B, either before or after doping of animpurity element which imparts n-type conductivity is performed underthe above mentioned condition, doping of an impurity element whichimparts an n-type conductivity may also be performed with anacceleration voltage of 70 to 120 keV in a state in which the mask 433is formed on the semiconductor layer 404. The concentration of theimpurity element which imparts an n-type conductivity in a portion 446which becomes an Loff region of the switching TFT can be suppressed inaccordance with the above process, and the concentration of the impurityelement which imparts n-type conductivity in portions 442 and 443, whichbecome Lov regions of the TFTs used in the driver circuit can beincreased. It is possible to lower the off current of the switching TFTby suppressing the concentration of the impurity element which impartsan n-type conductivity in the portion 446 which becomes the Loff regionof the switching TFT. Further, hot carriers generated in accordance witha high electric field in the vicinity of the drain and a cause of adegradation phenomenon due to the hot carrier effect can be prevented byincreasing the concentration of the n-type conductivity impartingimpurity element in the portion 443 which becomes the Lov region of then-channel TFT used in the driver circuit.

[0298] After removing the mask 453, source regions 447 and 448, drainregions 449 and 450, and Lov regions 451 and 452, having a conductivitytype which is the inverse of the above one conductivity type, are thenformed in the semiconductor layers 402 and 405 for forming the p-channelTFT, as shown in FIG. 24C. The second shape conducting layers 419 and422 are used as a mask with respect to the impurity element, and theimpurity regions are formed in a self-aligning manner. The semiconductorlayers 402 and 403, which form n-channel TFTs, are covered over theirentire surface areas by a resist masks 453 at this point. Phosphorus isadded in differing concentration to the source regions 447 and 448, thedrain regions 449 and 450, and the Lov regions 451 and 452, and iondoping is performed here using diborane (B₂H₆), so that impurity isadded to each of the regions with a concentration of 2×10²⁰ to 2×10²¹atoms/cm³.

[0299] Impurity regions (source regions, drain regions, Lov regions, andLoff regions) are formed in the respective semiconductor layers 402 to405 by the above processes. The second conducting layers 419 to 422overlapping the semiconductor layers function as gate electrodes.

[0300] A process of activating the impurity elements added to therespective semiconductor layers is then performed, with the aim ofcontrolling the conductivity type. Thermal annealing using an annealingfurnace is performed for this process. In addition, laser annealing andrapid thermal annealing (RTA) can also be applied. Thermal annealing isperformed with an oxygen concentration equal to or less than 1 ppm,preferably equal to or less than 0.1 ppm, in a nitrogen atmosphere at400 to 700° C., typically between 500 and 600° C. Heat treatment isperformed for 4 hours at 500° C. in Embodiment 8. However, for cases inwhich the wiring material used in the conducting layers 419 to 422 isweak with respect to heat, it is preferable to perform activation afterforming an interlayer insulating film (having silicon as its mainconstituent) in order to protect the wirings and the like.

[0301] In addition, heat treatment is performed for 1 to 12 hours at 300to 450° C. in an atmosphere containing between 3 and 100% hydrogen,performing hydrogenation of the semiconductor layers. This process isone of terminating dangling bonds in the semiconductor layers byhydrogen which is thermally excited. Plasma hydrogenation (usinghydrogen excited by a plasma) may also be performed as another means ofhydrogenation.

[0302] A first interlayer insulating film 455 is formed next from asilicon oxynitride film having a thickness of 100 to 200 nm. (FIG. 25A)A second interlayer insulating film 458 made from an organic insulatingmaterial is then formed on the first interlayer insulating film 455.

[0303] Contact holes are then formed in the gate insulating film 406,the first interlayer insulating film 455 and the second interlayerinsulating film 458, and source wirings 459 to 462 are formed to contactthe source regions 447, 435, 436, and 448 through the contact holes. Inthe same way, drain wirings 463 to 465 are further formed to contact thedrain regions 449, 439, 440 and 450. (FIG. 25B)

[0304] Note that it is preferable to form the contact holes by dryetching using CF₄ and O₂ when the gate insulating film 406, the firstinterlayer insulating film 455, and the second interlayer insulatingfilm 458 are SiO₂ films or SiON films. Further, for cases in which thegate insulating film 406, the first interlayer insulating film 455, andthe second interlayer insulating film 458 are organic resin films, it ispreferable to form the contact holes by dry etching using CHF₃ or by BHF(buffered hydrogen fluoride, HF+NH₄F). In addition, if the gateinsulating film 406, the first interlayer insulating film 455 and thesecond interlayer insulating film 458 are formed by different materials,it is preferable to change the method of etching and the etchant oretching gas type for each film. The contact holes may also be formed byusing the same etching method and the same etchant or etching gas.

[0305] A third interlayer insulating film 467 is formed next from anorganic resin. Organic resins such as polyimide, polyamide, acrylic, andBCB (benzocyclobutene) can be used. In particular, it is preferable touse acrylic, which has superior levelness, because the third interlayerinsulating film 467 is formed with a strong implication of leveling. Anacrylic film is formed in Embodiment 8 at a film thickness at whichsteps formed by the TFTs can be sufficiently leveled. The film thicknessis preferably from 1 to 5 μm (more preferably between 2 and 4 μm).

[0306] A contact hole for reaching the drain wiring 465 is formed nextin the third interlayer insulating film 467, and a pixel electrode 468is formed. An indium tin oxide (ITO) film is formed with a thickness of110 nm in Embodiment 8, and patterning is then performed, therebyforming the pixel electrode 468. Further, a transparent conducting filmin which between 2 and 20% zinc oxide (ZnO) is mixed with indium oxidemay also be used. The pixel electrode 468 becomes an anode of a lightemitting layer. (See FIG. 25C.)

[0307] A first bank 469 and a second bank 470 are formed next from aresin material. The first bank 469 and the second bank 470 are formed inorder to separate an organic compound layers and cathodes, which areformed later, of adjacent pixels. It is therefore preferable that thesecond bank 470 stick out farther horizontally than the first bank 469.Note that it is preferable that the combined thickness of the first bank469 and the second bank 470 be made on the order of 1 to 2 μm, but thereare no limitations on this thickness provided that the organic compoundlayers and the cathodes formed later of adjacent pixels can beseparated. Further, it is necessary to form the first bank 469 and thesecond bank 470 by an insulating film, and it is therefore possible touse materials such as an oxide or a resin, for example. The first bank469 and the second bank 470 may both be formed by the same material, andthey may also be formed by different materials. The first bank 469 andthe second bank 470 are formed in stripe shapes between pixels. Thefirst bank 469 and the second bank 470 may be formed on and along thesource wirings (source signal lines), and may be formed on and along thegate wirings (gate signal lines). Note that the first bank 469 and thesecond bank 470 may also be formed by a material in which a pigment ismixed into a resin. (See FIG. 26A.)

[0308] An organic compound layer 471 and a cathode (MgAg electrode) 472are formed next in succession without exposure to the atmosphere usingvacuum evaporation. Note that the film thickness of the organic compoundlayer 471 may be from 80 to 200 nm (typically between 100 and 120 nm),and that the film thickness of the cathode 472 may be from 180 to 300 nm(typically between 200 and 250 nm). Note also that, although only onepixel is shown in Embodiment 8, an organic compound layer which emitsred color light, an organic compound layer which emits green colorlight, and an organic compound layer which emits blue color light areformed at the same time at this point. Note that materials to form anorganic compound layer and a cathode is partially laminated on the bank470, however, in this specification, the materials are not included inthe organic compound layer 471 and the cathode 472.

[0309] The organic compound layer 471 and the cathode 472 are formed inorder for a pixel corresponding to the red color, a pixel correspondingto the green color, and a pixel corresponding to the blue color.However, the organic compound layer 471 lacks resistance with respect tosolutions, and therefore each color must be formed separately withoutusing a photolithography technique. It is preferable to use a metal maskand cover the pixels other than the desired pixel, and selectively formthe organic compound layer 471 and the cathode 472 in only the requiredportions.

[0310] Namely, first a mask is set so as to cover all of the pixelsexcept for those corresponding to the red color, and red colorlight-emitting organic compound layers are selectively formed using themask. Next, a mask is set so as to cover all of the pixels except forthose corresponding to the green color, and green color light-emittingorganic compound layers are selectively formed using the mask. Finally,a mask is set so as to cover all of the pixels except for thosecorresponding to the blue color, and blue color light-emitting organiccompound layers are selectively formed using the mask. Note that,although the use of all different masks is described here, the same maskmay also be reused. Further, it is preferable to perform processinguntil an organic compound layer and a cathode are formed on all ofpixels without releasing the vacuum.

[0311] Note that the organic compound layer 471 has a single layerstructure composed of only a light-emitting layer is shown in Embodiment8, but a structure having layers such as a hole transporting layer, ahole injecting layer, an electron transporting layer, and an electroninjecting layer in addition to the light-emitting layer may also be usedfor the organic compound layer. Various examples of these types ofcombinations have already been reported, and all such structures may beused. A known material can be used as the organic compound layer 471.Considering the driver voltage of a light emitting element, it ispreferable to use an organic material as the known material.

[0312] The cathode 472 is formed next. An example of using an MgAgelectrode as the cathode of an light emitting element is shown inEmbodiment 8, but it is also possible to use other known materials.

[0313] The active matrix substrate having the structure shown in FIG.26B is thus completed. Note that, after forming the first bank 469 andthe second bank 470, it is effective to perform processing in successionwithout exposure to the atmosphere up through to the formation of thecathode 472 by using a multi-chamber method (or an in-line method) thinfilm formation apparatus.

[0314] In Embodiment 8, a source region 504, a drain region 505, an Loffregion 506, an Lov region 507, and a channel forming region 508 arecontained in a semiconductor layer of a switching TFT 501. The Loffregion 506 is formed so as not to overlap with the gate electrode 421through the gate insulating film 406. Further, the Lov region 507 isformed so as to overlap with the gate electrode 421 through the gateinsulating film 406. This type of structure is extremely effective inreducing the off current.

[0315] Further, a single gate structure is used as the switching TFT 501in Embodiment 8, but the present invention may also have a double gatestructure or another type of multi-gate structure for the switching TFT.Two TFTs are substantially connected in series by using the double gatestructure, giving the advantage of additionally reducing the offcurrent.

[0316] Further, the switching TFT 501 is an n-channel TFT in Embodiment8, but a p-channel TFT may also be used.

[0317] A semiconductor layer of a current controlling TFT 502 contains asource region 510, a drain region 511, an Lov region 512, and a channelforming region 513. The Lov region 512 is formed so as to overlap withthe gate electrode 422 through the gate insulating film 406. Note thatthe current controlling TFT 502 does not have the Loff region inEmbodiment 8, but a structure having the Loff region may also be used.

[0318] Further, the current controlling TFT 502 is a p-channel TFT inEmbodiment 8, but it may also be an n-channel TFT.

[0319] Note that the active matrix substrate of Embodiment 8 shows anextremely high reliability, and its operational characteristics are alsoincreased, by arranging optimally structured TFT in not only the pixelportion, but also in the driver circuit portion.

[0320] First, a TFT having a structure in which hot carrier injection isreduced so as not to have a very large drop in operational speed is usedas an n-channel TFT 503 of a CMOS circuit forming the driver circuitportion. Note that circuits such as a shift register, a buffer, a levelshifter, and a sampling circuit (sample and hold circuits) are includedas the driver circuits here. Signal conversion circuits such as a D/Aconverter can also be included in the case of performing digital drive.

[0321] A semiconductor layer of the n-channel TFT 503 of the CMOScircuit in Embodiment 8 contains a source region 521, a drain region522, an Lov region 523, and a channel forming region 524.

[0322] Further, a semiconductor layer of a p-channel TFT 504 of the CMOScircuit contains a source region 531, a drain region 532, an Lov region533, and a channel forming region 534.

[0323] Note that, in practice, it is preferable to perform packaging(sealing) by a protecting film having high airtight characteristics andlittle outgassing (such as a laminate film or an ultraviolet hardenedresin film) or by a transparent sealing material after completing upthrough to the processes of FIG. 26B so as to have no exposure to theatmosphere. Further, if an inert gas is placed in the inside of thesealing material, and a drying agent (barium oxide, for example) isarranged inside of the sealing material, then the reliability of thelight emitting element is increased.

[0324] Further, a connector (flexible printed circuit, FPC) is attachedin order to connect the elements formed on the substrate, with terminalsextended from the circuits, to external signal terminals afterincreasing the airtight characteristics in accordance with the packagingprocess or the like. A manufactured product is thus completed. This typeof deliverable state is referred to as a light emitting devicethroughout this specification.

[0325] The widths of the gate electrodes in the direction of the channellength (referred to hereinafter as a width of the gate electrode) differas stated above in accordance with manufacturing processes of thepresent invention. Therefore, it is possible to make the ionimplantation within the semiconductor layers arranged under the firstgate electrode less than the ion concentration within the semiconductorlayers not arranged under the first gate electrode by utilizing thedifference in ion penetration depth, due to the difference of gateelectrode thickness, when performing ion injection using the gateelectrodes as masks.

[0326] Further, in order to form the Loff regions using a mask, only thewidth of Lov region needs to be controlled by etching. It becomes easyto control positions of the Lov regions and the Loff regions.

[0327] Note that although an example in which light emitted from theorganic compound layer is directed toward the substrate side isexplained in Embodiment 8, the present invention is not limited to this,and a structure in which light emitted from the organic compound layeris directed above the substrate may also be used. In this case, thecathode of the light emitting element becomes the pixel electrode, andit is preferable that the current controlling TFT be an n-channel TFT.

[0328] Note that although the case in which a pixel has a switching TFTand a current controlling TFT is explained in Embodiment 8, the presentinvention is not limited to this. Even when a pixel has three TFTs ormore, it is possible to apply the present embodiment.

[0329] The method of manufacturing a light emitting device according tothe present invention is not limited to the manufacturing methoddescribed in Embodiment 8 and other manufacturing methods can beutilized.

[0330] Note that it is possible to freely combine Embodiment 8 with anyof Embodiments 1 to 7.

Embodiment 9

[0331] A light emitting device manufactured by the present invention hassuperior visibility in bright locations in comparison to a liquidcrystal display device because it is a self-emission type device, andmoreover viewing angle is wide. Accordingly, it can be used as a displayportion for various electronic apparatuses. For example, it isappropriate to use the light emitting display device of the presentinvention as a display portion of a display device incorporating thelight emitting device in its casing having a diagonal equal to 30 inchesor greater (typically equal to 40 inches or greater) for appreciation ofTV broadcasts by large screen. The light emitting device of the presentinvention can be used as a display portion for various electronicapparatuses.

[0332] The following can be given as examples of such electronicapparatuses: a video camera; a digital camera; a goggle type display(head mounted display); a car navigation system; an audio reproducingdevice (such as a car audio system, an audio compo system); a notebookpersonal computer; a game equipment; a portable information terminal(such as a mobile computer, a mobile telephone, a mobile game equipmentor an electronic book); and an image playback device provided with arecording medium (specifically, a device which performs playback of arecording medium and is provided with a display which can display thoseimages, such as a digital video disk (DVD)). In particular, becauseportable information terminals are often viewed from a diagonaldirection, the wideness of the field of vision is regarded as veryimportant. Thus, it is preferable that the light emitting device isemployed. Examples of those electronic apparatuses are shown in FIGS. 27and 28.

[0333]FIG. 27A illustrates a portable information terminal whichincludes a display panel 2701 and an operation panel 2702. The displaypanel 2701 is connected with the operation panel 2702 at a connectionportion 2703. In the connection portion 2703, an angle θ between asurface provided with the display portion 2704 of the display panel 2701and a surface provided with an operation key 2706 of the operation panel2702 can be arbitrary varied.

[0334] The display panel 2701 includes the display portion 2704.Further, the portable information terminal shown in FIG. 27A has afunction as a telephone, and the display panel 2701 includes an audiooutput portion 2705, so that voice is outputted from the audio outputportion 2705. The light emitting device of the present invention can beutilized for the display portion 2704.

[0335] The operation panel 2702 includes an operation key 2706, a powerswitch 2707, an audio input portion 2708, and a CCD receiving portion2709. Note that although the operation key 2706 and the power switch2707 are provided separately in FIG. 27A, the power switch 2707 may beincluded in the operation key 2706.

[0336] In the audio input portion 2707, voice is inputted. The imageinputted at the CCD receiving portion 2709 is received in the portableinformation terminal as an electronic data.

[0337] Note that although the display panel 2701 includes the audiooutput portion 2705 and the operation panel includes the audio inputportion 2708 in FIG. 27A, the present embodiment is not limited to this.Namely, the display panel 2701 includes the audio input portion 2708,and the operation panel includes the audio output portion 2705. Further,the audio output portion 2705 and the audio input portion 2708 may beprovided in the display panel 2701, and the audio output portion 2705and the audio input portion 2708 may be provided in the operation panel2702.

[0338] Note that although the portable information terminal includes noantenna in FIG. 27A, an antenna may be provided, if necessary.

[0339]FIG. 27B illustrates a portable telephone, which includes a mainbody 2601, an audio output portion 2602, an audio input portion 2603, adisplay portion 2604, operation switches 2605, and an antenna 2606. Thelight emitting device in accordance with the present invention can beused as the display portion 2604. The display portion 2604 can reducepower consumption of the portable telephone by displaying white-coloredcharacters on a black-colored background.

[0340] The light emitting device of the present invention is veryeffective for the portable type electronic apparatus since powerconsumption can be reduced.

[0341]FIG. 28A illustrates a display device having a light emittingdevice which includes a frame 2001, a support table 2002, a displayportion 2003, or the like. The light emitting device of the presentinvention is applicable to the display portion 2003. The light emittingdevice is of the self-emission type and therefore requires no backlight. Thus, the display portion thereof can have a thickness thinnerthan that of the liquid crystal display device.

[0342]FIG. 28B illustrates a video camera which includes a main body2101, a display portion 2102, an audio input portion 2103, operationswitches 2104, a battery 2105, an image receiving portion 2106, or thelike. The light emitting device in accordance with the present inventioncan be used as the display portion 2102.

[0343]FIG. 28C illustrates one portion (the right-half piece) of ahead-mounted type electronic apparatus which includes a main body 2201,signal cables 2202, a head mount band 2203, a screen portion 2204, anoptical system 2205, a display portion 2206, or the like. The lightemitting device of the present invention is applicable to the displayportion 2206.

[0344]FIG. 28D illustrates an image reproduction apparatus provided witha recording medium (more specifically, a DVD reproduction apparatus),which includes a main body 2301, a recording medium (a DVD or the like)2302, operation switches 2303, a display portion (a) 2304, anotherdisplay portion (b) 2305, or the like. The display portion 2304(a) isused mainly for displaying image information, while the display portion2305(b) is used mainly for displaying character information. The lightemitting device in accordance with the present invention can be used asthese display portions 2304(a) and 2305(b). The image reproductionapparatus provided with a recording medium further includes a domesticgame equipment or the like.

[0345]FIG. 28E illustrates a goggle type display (head-mounted display)which includes a main body 2401, a display portion 2402, and an armportion 2403. The light emitting device in accordance with the presentinvention can be used to the display portion 2402.

[0346]FIG. 28F illustrates a personal computer which includes a mainbody 2501, a frame 2502, a display portion 2503, a key board 2504, orthe like. The light emitting device in accordance with the presentinvention can be used as the display portion 2503. Note that if emissionluminance of an organic material becomes higher in the future, lightincluding outputted image information is enlarged to be projected bymeans of lenses or the like, thereby applying to a front-type or arear-type projector.

[0347] The aforementioned electronic apparatuses are more likely to beused for display information distributed through a telecommunicationpath such as Internet, a CATV (cable television system), and inparticular likely to display moving picture information. The lightemitting device is suitable for displaying moving pictures since theorganic material can exhibit high response speed.

[0348] Since a light emitting portion of the light emitting deviceconsumes power, it is desirable to display information in such a mannerthat the light emitting portion therein becomes as small as possible.Accordingly, when the light emitting device is applied to a displayportion which mainly displays character information, e.g., a displayportion of a portable information terminal, and more particular, aportable telephone or a car audio reproducing equipment, it is desirableto drive the light emitting display device so that the characterinformation is formed by a light-emitting portion while a non-emissionportion corresponds to the background.

[0349] As set forth above, the present invention can be appliedvariously to a wide range of electronic apparatuses in all fields. Notethat it is possible to freely combine Embodiment 9 with any ofEmbodiments 1 to 8.

Embodiment 10

[0350] In this embodiment, a further specific structure of a thirdstructure of the present invention and a change in brightness due to atemperature will be explained with measured values.

[0351]FIG. 29A shows a connection state of a light emitting element fora monitor, which is included in a light emitting device of thisembodiment. Reference numerals 702, 703, 704 and 705 represent a bufferamplifier, a monitoring light emitting element, a constant currentsource, and one of light emitting elements in a pixel portion,respectively.

[0352] In this embodiment, an output terminal of the buffer amplifier702 is connected with a source region or a drain region, of a currentcontrolling TFT (not shown). Also, the light emitting element 705 in thepixel portion is connected with an output terminal of the bufferamplifier 702.

[0353] Also, in FIG. 29A, although an anode of the light emittingelement 705 in the pixel portion is used as a pixel electrode, thisembodiment is not limited to such a structure. A cathode may be used asa pixel electrode.

[0354] The constant current source 704 of this embodiment has anamplifier, a variable resistor and a bipolar transistor. References V1and V2 represent a predetermined voltage to be applied, a relationship(a voltage applied to an anode<V2<V1) is satisfied. By the way, therelationship among the voltage applied to the anode, V2, and V1 ischanged depending on whether an anode is used as a pixel electrode or acathode is used as pixel electrode. In order to flow a forward biascurrent into a light emitting element, the relationship among thevoltage applied to the anode, V2, and V1 is appropriately set. Also, theconstant current source 704 is not limited to the structure as shown inFIG. 29A, a well-known constant current source can be used.

[0355] An output terminal of the constant current source 704 isconnected with a pixel electrode of the monitoring light emittingelement 703. By the way, when an anode of the light emitting element 705in the pixel portion is used as a pixel electrode, an anode of themonitoring light emitting element 703 is also used as a pixel electrode.To the contrary, when a cathode of the light emitting element 705 in thepixel portion is used as a pixel electrode, a cathode of the monitoringlight emitting element 703 is also used as a pixel electrode. In FIG.29A, the anode of the monitoring light emitting element 703 is used as apixel electrode.

[0356] When the output terminal of the constant current source 704 isconnected with the pixel electrode of the monitoring light emittingelement 703 and thus a current flows into the monitoring light emittingelement 703, its value is always kept constant. And then, when atemperature of a organic compound layer included in the light emittingelement is changed, although an amount of a current flowing into themonitoring light emitting element 703 is not changed, a potential of thepixel electrode of the monitoring light emitting element 703, which isconnected with the constant current source 704, is changed.

[0357] On the other hand, the buffer amplifier 702 has two inputterminals and one output terminal, one of the two input terminals is anon-inverted input terminal (+), and the other is an inverted inputterminal (−). A potential of the pixel electrode of the monitoring lightemitting element 703 is provided with the non-inverted input terminal ofthe buffer amplifier 702.

[0358] The buffer amplifier 702 is a circuit for suppressing a change inthe potential of the pixel electrode of the monitoring light emittingelement 703, which is connected with the constant current source 704,due to a load such as a wiring capacitance or the like. Thus, thepotential provided with the non-inverted input terminal of the bufferamplifier 702 is output from the output terminal without the change dueto a load such as a wiring capacitance or the like, and provided withthe pixel electrode of the light emitting element 705 in the pixelportion. As a result, a current flowing into the monitoring lightemitting element 703 is equal to a current flowing into the lightemitting element 705 in the pixel portion.

[0359] Then, even when a temperature of an organic compound layer of,the monitoring light emitting element 703 or the light emitting element705 in the pixel portion is changed depending on a change in an ambiancetemperature, a constant current flows into each light emitting element.Thus, even when the ambiance temperature of the light emitting devicerises, an increase in power consumption of the light emitting device canbe suppressed.

[0360]FIG. 29B shows a change in measurement values of brightness due toa temperature, of the light emitting element 705 in the pixel portion ofthe light emitting device having the structure as shown in FIG. 29A. Bythe way, a graph (corrected) relates to the measurement values in thelight emitting device of the present invention, and a graph (notcorrected) relates to the measurement values in the light emittingdevice without the third structure of the present invention.

[0361] As can be cleared from FIG. 29A, in the graph (not corrected),the brightness is increased depending on the rise of the temperature.However, in the graph (corrected), even when the temperature rises, thebrightness is almost kept constant. Since a current and a brightness arein a proportional relation, in the light emitting device of the presentinvention, even when the temperature rises, a current can be keptconstant, and the increase in the power consumption can be suppressed.

[0362] Also, in a light emitting element, a decrease in brightness iscaused by deterioration of an organic light emitting layer. Here, evenif the deterioration is caused in the same level, a decrease amount inbrightness in the case where a current flowing between a cathode and ananode is kept constant is smaller than that in the case where a voltageapplied between the cathode and the anode is kept constant. Thus, sincea current flowing into the light emitting element can be kept constantin the light emitting device of the present invention, a decrease inbrightness, due to deterioration can be suppressed.

[0363] This embodiment can be arbitrarily combined with the structuresof Embodiments 1 to 9 with respect to the operation.

[0364] As described in the above, in accordance with the first structureof the present invention, the magnitude of a current to flow through thelight emitting element can be suppressed to some degree, therebyresulting in a reduced power consumption of the light emitting device.In accordance with the second structure of the present invention, thenumber of bits of the digital video signal to be input into the pixelsis reduced, and therefore, the required number of writing the digitalvideo signal by the source signal line driver circuit and a gate signalline driver circuit can be reduced. Thus, power consumption of thesource signal line driver circuit and the gate signal line drivercircuit can be reduced, thereby resulting in a reduced power consumptionof the light emitting device. In accordance with the third structure ofthe present invention, the magnitude of a current to flow through alight emitting element of a pixel is maintained at a constant level,even when a temperature of the organic compound layer changes. Thus,power consumption of the light emitting device can be prevented fromincreasing even when an environmental temperature of the light emittingdevice increases, which in turn can maintain the brightness at aconstant level.

[0365] In accordance with the first, second, and third structures of thepresent invention as described in the above, it is possible to suppressthe power consumption of a light emitting device and an electronicapparatus which employs the light emitting device. It should be notedthat only either one of the first through third structures is requiredto be included in the present invention, although two or all of thefirst through third structures may be included.

What is claimed is:
 1. A display device comprising: a plurality ofpixels, wherein a polarity of a video signal to be input into theplurality of pixels is inverted, thereby resulting in brightness of theplurality of pixels being changed.
 2. A display device according toclaim 1 , wherein said display device is a light emitting device.
 3. Adisplay device according to claim 1 , wherein said display device is oneselected from the group consisting of a video camera, an imagereproduction apparatus, a head mount display, a portable telephone, anda portable information terminal.
 4. A display device comprising: aplurality of pixels; and a source signal line driver circuit, whereinsaid source signal line driver circuit comprises a switching circuit forswitching a polarity of an output signal, and a polarity of a videosignal input to said switching circuit is inverted by means of a shiftsignal to be input into said switching circuit and a resultant signal isthen input into said plurality of pixels.
 5. A display device accordingto claim 4 , wherein: said switching circuit comprises an inverter, afirst analog switch, and a second analog switch, said video signal inputinto said switching circuit is input into an input terminal of saidfirst analog switch through said inverter, said video signal input intosaid switching circuit is input into an input terminal of said secondanalog switch, said shift signal is input into a first control inputterminal of said first analog switch and a second control input terminalof said second analog switch, a signal obtained by inverting a polarityof said shift signal is input into a second control input terminal ofsaid first analog switch and a second control input terminal of saidfirst analog switch, and signals output from output terminals of saidfirst analog switch and said second analog switch are output from saidswitching circuit.
 6. A display device according to claim 4 , wherein:said switching circuit comprises an inverter, a first NAND, a secondNAND, and a third NOR, said first NAND is supplied with said videosignal through said inverter and said shift signal, said second NAND issupplied with said video signal and a signal obtained by inverting apolarity of said shift signal, a signal output from said first NAND anda signal output from said second NAND are input into said third NOR, anda signal output from said third NOR is output from said switchingcircuit.
 7. A display device according to claim 4 , wherein said displaydevice is a light emitting device.
 8. A display device according toclaim 4 , wherein said display device is one selected from the groupconsisting of a video camera, an image reproduction apparatus, a headmount display, a portable telephone, and a portable informationterminal.
 9. A display device comprising: a plurality of pixels, eachcomprising a light emitting element; and a source signal line drivercircuit, wherein said source signal line driver circuit comprises ashift register, one or more latches, and a switching circuit, and apolarity of a digital video signal input from said one or more latchesinto said switching circuit is inverted by means of a shift signal to beinput into said switching circuit and a resultant signal is then inputinto the plurality of pixels.
 10. A display device according to claim 9, wherein: said switching circuit comprises an inverter, a first analogswitch, and a second analog switch, said video signal input into saidswitching circuit is input into an input terminal of said first analogswitch through said inverter, said video signal input into saidswitching circuit is input into an input terminal of said second analogswitch, said shift signal is input into a first control input terminalof said first analog switch and a second control input terminal of saidsecond analog switch, a signal obtained by inverting a polarity of saidshift signal is input into a second control input terminal of said firstanalog switch and a second control input terminal of said first analogswitch, and signals output from output terminals of said first analogswitch and said second analog switch are output from said switchingcircuit.
 11. A display device according to claim 9 , wherein: saidswitching circuit comprises an inverter, a first NAND, a second NAND,and a third NOR, said first NAND is supplied with said video signalthrough said inverter and said shift signal, said second NAND issupplied with said video signal and a signal obtained by inverting apolarity of said shift signal, a signal output from said first NAND anda signal output from said second NAND are input into said third NOR, anda signal output from said third NOR is output from said switchingcircuit.
 12. A display device according to claim 9 , wherein saiddisplay device is a light emitting device.
 13. A display deviceaccording to claim 9 , wherein said display device is one selected fromthe group consisting of a video camera, an image reproduction apparatus,a head mount display, a portable telephone, and a portable informationterminal.
 14. A display device comprising: a plurality of pixels, eachcomprising a light emitting element, and a source signal line drivercircuit, wherein said source signal line driver circuit comprises ashift register, one or more latches and a switching circuit, a polarityof a digital video signal input from said one or more latches into saidswitching circuit is inverted by means of a shift signal to be inputinto said switching circuit and a resultant signal is then input intothe plurality of pixels, and an average of a time period during whichall of the light emitting elements emit light in one frame period isequal to or less than a half of the maximum value of the time periodduring which all of the light emitting elements emit light in one frameperiod.
 15. A display device according to claim 14 , wherein: saidswitching circuit comprises an inverter, a first analog switch, and asecond analog switch, said video signal input into said switchingcircuit is input into an input terminal of said first analog switchthrough said inverter, said video signal input into said switchingcircuit is input into an input terminal of said second analog switch,said shift signal is input into a first control input terminal of saidfirst analog switch and a second control input terminal of said secondanalog switch, a signal obtained by inverting a polarity of said shiftsignal is input into a second control input terminal of said firstanalog switch and a second control input terminal of said first analogswitch, and signals output from output terminals of said first analogswitch and said second analog switch are output from said switchingcircuit.
 16. A display device according to claim 14 , wherein: saidswitching circuit comprises an inverter, a first NAND, a second NAND,and a third NOR, said first NAND is supplied with said video signalthrough said inverter and said shift signal, said second NAND issupplied with said video signal and a signal obtained by inverting apolarity of said shift signal, a signal output from said first NAND anda signal output from said second NAND are input into said third NOR, anda signal output from said third NOR is output from said switchingcircuit.
 17. A display device according to claim 14 , wherein saiddisplay device is a light emitting device.
 18. A display deviceaccording to claim 14 , wherein said display device is one selected fromthe group consisting of a video camera, an image reproduction apparatus,a head mount display, a portable telephone, and a portable informationterminal.
 19. A display device comprising: a plurality of pixels, and asource signal line driver circuit, wherein among a digital video signalto be input into said source signal line driver circuit, only moresignificant bits are input into said plurality of pixels.
 20. A displaydevice according to claim 19 , wherein said display device is a lightemitting device.
 21. A display device according to claim 19 , whereinsaid display device is one selected from the group consisting of a videocamera, an image reproduction apparatus, a head mount display, aportable telephone, and a portable information terminal.
 22. A displaydevice comprising: a pixel portion comprising a plurality of pixels, anda source signal line driver circuit comprising a shift register, a firstlatch, a second latch, and a clock signal control circuit,, wherein aclock signal is input into said shift register through said clock signalcontrol circuit to thereby output a timing signal from said shiftregister, a video signal is input into and held at said first latch bysaid timing signal, said video signal held at said first latch is inputinto and held at said second latch by a latch signal, said video signalinput into and held at said second latch is input into said plurality ofpixels, and said clock signal control circuit reduces the number of bitsof said digital video signal to be input into and held at said firstlatch by supplying a constant fixed electrical potential instead of saidclock signal to said shift register for a constant period of time.
 23. Adisplay device according to claim 22 , wherein said clock signal controlcircuit comprises a NAND and an inverter, a clock signal and a selectionsignal are input into said NAND, and a signal output from said NAND isoutput from said clock signal control circuit through said inverter. 24.A display device according to claim 22 , wherein said clock signalcontrol circuit comprises a first analog switch, a second analog switch,and an inverter, a selection signal is input through said inverter intoa second control input terminal of said first analog switch and a firstcontrol input terminal of said second analog switch, said selectionsignal is input into a first control input terminal of said first analogswitch and a second control input terminal of said second analog switch,a clock signal is input into an input terminal of said first analogswitch, a fixed electrical potential is supplied to an input terminal ofthe second analog switch, and signals output from output terminals ofsaid first analog switch and said second analog switch are output fromsaid clock signal control circuit.
 25. A display device according toclaim 22 , wherein said display device is a light emitting device.
 26. Adisplay device according to claim 22 , wherein said display device isone selected from the group consisting of a video camera, an imagereproduction apparatus, a head mount display, a portable telephone, anda portable information terminal.
 27. A display device comprising: apixel portion comprising a plurality of pixels, and a source signal linedriver circuit comprising a shift register, a first latch, a secondlatch, and a timing signal control circuit, wherein a timing signaloutput from said shift register is input into said first latch throughsaid timing signal control circuit, a video signal is input into andheld at said first latch by said timing signal input into said firstlatch, said video signal held at said first latch is input into and heldat said second latch by a latch signal, said video signal input into andheld at said second latch is input into said plurality of pixels, andsaid timing signal control circuit reduces the number of bits of saidvideo signal to be input into and held at said first latch by supplyingto said first latch a constant fixed electrical potential instead ofsaid timing signal output from said shift register for a constant periodof time.
 28. A display device according to claim 27 , wherein saidtiming signal control circuit comprises a NAND and an inverter, a timingsignal and a selection signal are input into said NAND, and a signaloutput from said NAND is output from said timing signal control circuitthrough said inverter.
 29. A display device according to claim 27 ,wherein said timing signal control circuit comprises a first analogswitch, a second analog switch, and an inverter, a selection signal isinput through said inverter into a second control input terminal of saidfirst analog switch and a first control input terminal of said secondanalog switch, the selection signal is input into a first control inputterminal of said first analog switch and a second control input terminalof said second analog switch, said timing signal is input into an inputterminal of said first analog switch, a fixed electrical potential issupplied to an input terminal of said second analog switch, and signalsoutput from output terminals of said first analog switch and said secondanalog switch are output from said timing signal control circuit.
 30. Adisplay device according to claim 27 , wherein said display device is alight emitting device.
 31. A display device according to claim 27 ,wherein said display device is one selected from the group consisting ofa video camera, an image reproduction apparatus, a head mount display, aportable telephone, and a portable information terminal.
 32. A displaydevice comprising: a pixel portion comprising a plurality of pixels, anda source signal line driver circuit comprising a shift register, a firstlatch, a second latch, and a start pulse signal control circuit, whereina start pulse signal is input into said shift register through saidstart pulse signal control circuit to thereby output a timing signalfrom said shift register, a video signal is input into and held at saidfirst latch by the timing signal, said video signal held at said firstlatch is input into and held at said second latch by a latch signal,said video signal input into and held at said second latch is input intosaid plurality of pixels, and said start pulse signal control circuitreduces the number of bits of said video signal to be input into andheld at said first latch by supplying to said shift register a constantfixed electrical potential instead of said start pulse for a constantperiod of time.
 33. A display device according to claim 32 , whereinsaid start pulse signal control circuit comprises a NAND and aninverter, a start pulse signal and a selection signal are input intosaid NAND, and a signal output from said NAND is output from the startpulse signal control circuit through said inverter.
 34. A display deviceaccording to claim 32 , wherein said start pulse signal control circuitcomprises a first analog switch, a second analog switch, and aninverter, a selection signal is input through said inverter into asecond control input terminal of said first analog switch and a firstcontrol input terminal of said second analog switch, said selectionsignal is input into a first control input terminal of said first analogswitch and a second control input terminal of said second analog switch,a start pulse signal is input into an input terminal of said firstanalog switch, a fixed electrical potential is supplied to an inputterminal of said second analog switch, and signals output from outputterminals of said first analog switch and said second analog switch areoutput from said start pulse signal control circuit.
 35. A displaydevice according to claim 32 , wherein said display device is a lightemitting device.
 36. A display device according to claim 32 , whereinsaid display device is one selected from the group consisting of a videocamera, an image reproduction apparatus, a head mount display, aportable telephone, and a portable information terminal.
 37. A displaydevice comprising: a plurality of pixels comprising a plurality of lightemitting elements, and a monitoring light emitting element, wherein avariation in a current to flow through said plurality of light emittingelements is reduced by means of temperature characteristics of saidmonitoring light emitting element.
 38. A display device according toclaim 37 , wherein said display device is a light emitting device.
 39. Adisplay device according to claim 37 , wherein said display device isone selected from the group consisting of a video camera, an imagereproduction apparatus, a head mount display, a portable telephone, anda portable information terminal.
 40. A display device comprising: apixel portion comprising a plurality of pixels, each pixels having athin film transistor and a light emitting element; a buffer amplifier; amonitoring light emitting element; and a constant current source,wherein each of said monitoring light emitting element and said lightemitting element comprises a first electrode, a second electrode, and anorganic compound layer interposed therebetween, said first electrode ofsaid monitoring light emitting element is connected to said constantcurrent source, and connected to a non-inverted input terminal of saidbuffer amplifier, and an output terminal of said buffer amplifier isconnected to said first electrode of said light emitting element.
 41. Adisplay device according to claim 40 , wherein said display device is alight emitting device.
 42. A display device according to claim 40 ,wherein said display device is one selected from the group consisting ofa video camera, an image reproduction apparatus, a head mount display, aportable telephone, and a portable information terminal.
 43. A displaydevice comprising: a pixel portion comprising a plurality of pixels,each pixels having a thin film transistor and a light emitting element;a buffer amplifier; a monitoring light emitting element; a constantcurrent source; and an adding circuit, wherein each of said monitoringlight emitting element and said light emitting element comprises a firstelectrode, a second electrode, and an organic compound layer interposedtherebetween, said first electrode of said monitoring light emittingelement is connected to said constant current source, and is connectedto a non-inverted input terminal of the buffer amplifier, an outputterminal of said buffer amplifier is connected to an input terminal ofsaid adding circuit, an output terminal of said adding circuit isconnected to said first electrode of said light emitting element, and aconstant potential difference is maintained between said input terminaland said output terminal of said adding circuit.
 44. A display deviceaccording to claim 43 , wherein said display device is a light emittingdevice.
 45. A display device according to claim 43 , wherein saiddisplay device is one selected from the group consisting of a videocamera, an image reproduction apparatus, a head mount display, aportable telephone, and a portable information terminal.